Fs Multiplier Register (0x04) - 2.0 English

SMPTE UHD-SDI Receiver Subsystem Product Guide

Document ID
PG290
Release Date
2022-04-26
Version
2.0 English

Program this register to specify the multiplier value of the aud_clk.

Table C-4: Fs Multiplier Register

Name

Default
Value

Access

Description

RSVD

[31:16]

Multi Value

0x180

RW

[15:0]

Specify the multiplier value of the aud_clk. For example, for Fs = 48 kHz, the supplied aud_clk is 18.432 MHz, then this register should be programmed with a value of 384. i.e. 48 kHz * 384 = 18.432 MHz