Functional Description - 2.0 English

SMPTE UHD-SDI Receiver Subsystem Product Guide

Document ID
PG290
Release Date
2022-04-26
Version
2.0 English

The SD interface to the audio extractor consists of data streams, mode and status signals from the SMPTE UHD-SDI RX Subsystem. The audio interface is a 32-bit AXI4-Stream master bus. This Figure shows the top level block diagram of the SDI audio extractor in 32 channel configuration.

Figure 3-2: SDI Audio Extractor Block Diagram

X-Ref Target - Figure 3-2

X21285-pg290-audio-extctr-block.jpg

In SD-SDI mode, as per SMPTE ST 272, up to 16 channels of audio are extracted from data stream 1 (Y Video In). In HD-SDI mode, as per SMPTE ST 299-1, up to 16 channels of audio are extracted from data stream 1 and 2. In 3G-SDI, 6G-SDI and 12G-SDI modes, as per SMPTE ST 299-1 and SMPTE ST 299-2, up to 32 channels of audio are extracted from data streams 1, 2, 3, and 4. Audio control packets are extracted from data stream 1 and 3 (Y Video In) and data packets are extracted from data stream 2 and 4 (C B C R Video In).

The Xilinx AXI4-Stream audio interface carries audio samples in Audio Engineering Society (AES3) format. The data width over the AXI4-Stream audio interface is fixed at 32 bits to carry one AES3 sub-frame as shown in the following figure.

Figure 3-3: AES3 Subframe Format with 24-Bit Audio Sample

X-Ref Target - Figure 3-3

Subframe_Format_with_24-Bit_Audio_Sample.png

The TID indicates the channel number of the audio sample data.

This Figure shows the interface timing diagram for the audio extractor core.

Figure 3-4: Audio Extract Timing Diagram

X-Ref Target - Figure 3-4

pg290-audio-extract-interface-timingi_IHFB2C_t.jpg