Table 2-16: GLBL_IER Register Bit Mapping Bits Name Access Default Value Description 31:1 Reserved RO 0 Reserved 0 GLBL_INTRUPT_EN R/W 0 Master enable for the device interrupt output to the system 1: Enabled—the corresponding Interrupt Enable register (IER) bits are used to generate interrupts 0: Disabled—Interrupt generation blocked irrespective of IER bits