Interrupt Enable Register (IER) (0x14) - 2.0 English

SMPTE UHD-SDI Receiver Subsystem Product Guide

Document ID
PG290
Release Date
2022-04-26
Version
2.0 English

This register allows you to selectively generate an interrupt at the output port for each error/status bit in the ISR. An IER bit set to 0 does not inhibit an error/status condition from being captured, but inhibits it from generating an interrupt.

Table 2-18: IER bit mapping

Bits

Name

Access

Default Value

Description

31:11

Reserved

RO

0

Set bits in this register to 1 to

generate the required interrupts. Set to 0 to disable the interrupt.

For a description of the specific interrupt you are enabling/disabling in this register see the ISR descriptions in Table: ISR bit mapping .

10

UNDERFLOW_INTR_EN

R/W

0

9

OVERFLOW_INTR_EN

R/W

0

8:3

Reserved

RO

0

2

VSYNC_VALID_IE

R/W

0

1

VIDEO_UNLOCK_INTR_EN

R/W

0

0

VIDEO_LOCK_INTR_EN

R/W

0