Keep It Registered - 2.0 English

SMPTE UHD-SDI Receiver Subsystem Product Guide

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2.0 English

To simplify timing and increase system performance in an FPGA design, keep all inputs and outputs registered with flip-flops between the user application and the subsystem. Registering signals might not be possible for all paths, but doing so simplifies timing analysis and makes it easier for the Xilinx tools to place-and-route the design.