MODULE_CTRL Register (0x04) - 2.0 English

SMPTE UHD-SDI RX Subsystem (PG290)

Document ID
PG290
Release Date
2023-05-17
Version
2.0 English

This register provides control of the SMPTE UHD-SDI RX IP core and core functional modes.

Table 2-15: MODULE_CTRL Register Bit Mapping

Bits

Name

Access

Default Value

Description

31:19

Reserved

RO

0

Reserved

18:16

RX_FORCED_MODE

R/W

0

RX forced mode

3’b000: HD mode

3’b001: SD mode

3’b010: 3G mode

3’b100: 6G mode

3’b101: 12G mode with 11.88 Gbps line rate

3’b110: 12G mode with 11.88/1.001 Gbps line rate

15:14

Reserved

RO

0

Reserved

13:8

RX_MODE_EN

R/W

0

RX mode enable

Bit8: enable HD-SDI mode

Bit9: enable SD-SDI mode

Bit10: enable 3G-SDI mode

Bit11: enable 6G-SDI mode

Bit12: enable 12G-SDI 11.88 Gbps mode

Bit13: enable 12G-SDI 11.88/1.001 Gbps mode

7:6

Reserved

RO

2’b01

Reserved

5

RX_MODE_DET_EN

R/W

0

RX mode detection enable

4

RX_FRM_EN

R/W

0

RX frame enable

3:0

Reserved

RO

0

Reserved