M_AXIS_CTRL_SB_RX Interface Ports - 2.0 English

M_AXIS_CTRL_SB_RX__tready

I

Core Ready

M_AXIS_CTRL_SB_RX_tvalid

O

Data valid

M_AXIS_CTRL_SB_RX_tdata[31:0]

O

Sideband signal information from transceiver block

bit 2:0: rx_mode
bit 3: rx_mode_locked
bit 4: rx_level_b_3g
bit 5: rx_ce
bit 31–6: unused