Navigating Content By Design Process - 2.0 English

SMPTE UHD-SDI Receiver Subsystem Product Guide

Document ID
PG290
Release Date
2022-04-26
Version
2.0 English

Xilinx documentation is organized around a set of standard design processes to help you find relevant content for your current development task. This document covers the following design processes:

Hardware, IP, and Platform Development: Creating the PL IP blocks for the hardware platform, creating PL kernels, subsystem functional simulation, and evaluating the Vivado® timing, resource and power closure. Also involves developing the hardware platform for system integration. Topics in this document that apply to this design process include:

° Port Descriptions

° Software Structure

° Clocking

° Resets

° Customizing and Generating the Subsystem

° Example Design

For driver information, see the Xilinx GIT hub .

For IP patch information, see the SMPTE UHD-SDI Receiver (RX) Subsystem Release Notes and Known Issues AR# 68766 .