This register allows you to enable and disable the SMPTE UHD-SDI RX IP core and apply a soft reset during core operation.
Table 2-14:
RST_CTRL Register Bit Mapping
|
Bits
|
Name
|
Access
|
Default Value
|
Description
|
|
31:13
|
Reserved
|
RO
|
0
|
Reserved
|
|
12:10
|
SDIRX_BRIDGE_CH_FORMAT_AXI
|
R/W
|
0
|
Selection of chroma format
001 -
YCbCr
4:4:4 format selection
Others - Reserved
|
|
9
|
VID_IN_AXI4S_MOD_EN
|
R/W
|
0
|
Enable bit for Video-in-AXI4S core
1 – Video-in-AXI4S core is enabled
0 – Video-in-AXI4S core is disabled
This bit is available only in AXI4-Stream is selected as the video interface
|
|
8
|
SDIRX_BRIDGE_EN
|
R/W
|
0
|
Enable bit for SDI RX Bridge
1 – SDI RX bridge is enabled
0 – SDI RX bridge is disabled
This bit is not available if Native SDI is selected as video interface
|
|
7:4
|
Reserved
|
RO
|
0
|
Reserved
|
|
3
|
RST_EDH_ERRCNT
|
R/W
|
0
|
Clear rx_edh_errcnt register
|
|
2
|
RST_CRC_ERRCNT
|
R/W
|
0
|
Clear rx_crc_errcnt register
|
|
1
|
SRST
|
R/W
|
0
|
Soft reset for SDI RX IP core
Writing a 1 to this bit resets all registers of the SDI RX IP.
|
|
0
|
SDIRX_IP_EN
|
R/W
|
0
|
Enable bit for SDI RX IP core
1 – SDI RX IP core is enabled
0 – SDI RX IP core is disabled
|