RX_ST352_VALID Register (0x18) - 2.0 English

SMPTE UHD-SDI Receiver Subsystem Product Guide

Document ID
PG290
Release Date
2022-04-26
Version
2.0 English
Table 2-19: RX_ST352_VALID Register Bit Mapping

Bits

Name

Access

Default
Value

Description

31:16

Reserved

RO

0

Reserved

15

RX_ST352_VLD_DS16

RO

0

Asserted high when ST352 is valid on data stream 16 (C stream of Channel 7)

14

RX_ST352_VLD_DS14

RO

0

Asserted high when ST352 is valid on data stream 14 (C stream of Channel 6)

13

RX_ST352_VLD_DS12

RO

0

Asserted high when ST352 is valid on data stream 12 (C stream of Channel 5)

12

RX_ST352_VLD_DS10

RO

0

Asserted high when ST352 is valid on data stream 10 (C stream of Channel 4)

11

RX_ST352_VLD_DS8

RO

0

Asserted high when ST352 is valid on data stream 8 (C stream of Channel 3)

10

RX_ST352_VLD_DS6

RO

0

Asserted high when ST352 is valid on data stream 6 (C stream of Channel 2)

9

RX_ST352_VLD_DS4

RO

0

Asserted high when ST352 is valid on data stream 4 (C stream of Channel 1)

8

RX_ST352_VLD_DS2

RO

0

Asserted high when ST352 is valid on data stream 2 (C stream of Channel 0)

7

RX_ST352_VLD_DS15

RO

0

Asserted high when ST352 is valid on data stream 15 (Y stream of Channel 7)

6

RX_ST352_VLD_DS13

RO

0

Asserted high when ST352 is valid on data stream 13 (Y stream of Channel 6)

5

RX_ST352_VLD_DS11

RO

0

Asserted high when ST352 is valid on data stream 11 (Y stream of Channel 5)

4

RX_ST352_VLD_DS9

RO

0

Asserted high when ST352 is valid on data stream 9 (Y stream of Channel 4)

3

RX_ST352_VLD_DS7

RO

0

Asserted high when ST352 is valid on data stream 7 (Y stream of Channel 3)

2

RX_ST352_VLD_DS5

RO

0

Asserted high when ST352 is valid on data stream 5 (Y stream of Channel 2)

1

RX_ST352_VLD_DS3

RO

0

Asserted high when ST352 is valid on data stream 3 (Y stream of Channel 1)

0

RX_ST352_VLD_DS1

RO

0

Asserted high when ST352 is valid on data stream 1 (Y stream of Channel 0)