Register Space - 2.0 English

SMPTE UHD-SDI Receiver Subsystem Product Guide

Document ID
PG290
Release Date
2022-04-26
Version
2.0 English

The Audio Pattern Generator (PatGen) IP register space is shown in Table: Audio Pattern Generator Register Space .

Table C-2: Audio Pattern Generator Register Space

Reg Offset

Name

Reg Description

0x00

Control Register

Control register

0x04

Fs Multiplier

Register to specify Fs multiplier

0x08

Patgen Configuration

PatGen configuration such as channels, pattern, sampling and data width

0x0C

Silence time register

Specify any silence time to create a beep pattern

0x10-0x24

Channel Status Bits

Specify the 192 bits channel status

0x28-0x3C

User Status bits

Specify the 192 bits user bits

0x40

Validity register

Set the validity bit for samples

0x44

Checker Status

To check the checker result

0x48

Valid sample counter

Counts the number valid samples that were checked

0x4C

Number of samples
missed counter

Counts number data mismatches that occurred

0x50

Data received

Incoming data sample register

0x54

Previous data

Previous sampled data register

Note: The AXI4-Lite write access register is updated by the 32-bit AXI Write Data (*_wdata) signal, and is not impacted by the AXI Write Data Strobe (*_wstrb) signal. For a Write, both the AXI Write Address Valid (*_awvalid) and AXI Write Data Valid (*_wvalid) signals should be asserted together.