Revision History - 2.0 English

SMPTE UHD-SDI Receiver Subsystem Product Guide

Document ID
PG290
Release Date
2022-04-26
Version
2.0 English

The following table shows the revision history for this document.

Date

Version

Revision

04/26/2022

2.0

Added parameters to select HFR and YCbCr444 support to reduce resource count.

06/30/2021

2.0

Added 12G/6G HFR resolutions for 10 bit for AXI Interface subsystem configuration.

Updated unsupported feature section

Update TS_det register configuration for HFR

Updated This Figure

Updated Table: HFR Video Resolutions Tested in Simulation for 10 Bits/Component for Native SDI mode

Added Table: HFR Video Resolutions Tested in Simulation for 10 Bits/Component in AXI- stream interface Sub-system configuration:

01/11/2021

2.0

Added HLG HDR feature

Added Versal ACAP Block Automation in UHD-SDI RX Subsystem section

Added VCK190 SMPTE UHD-SDI Audio-Video Pass-Through Example Design section

10/05/2020

2.0

Updated Features for 12-bit support and HFR support added in design

Updated Unsupported Features

Updated Reference clock selection in Clocking section for integer and fractional frame rates

Added Table: HFR Video Resolutions Tested in Simulation for 10 Bits/Component for Native SDI mode for tested HFR resolutions in simulation Video Resolutions

Added Table: Non-HFR Tested Video Resolutions for 12 Bits/Component for tested 12-bit resolutions in simulation Video Resolutions

11/08/2019

2.0

Added Table A-1, Table A-5, Table C-9, and Table C-10

Updated Table 2-8, Table 2-14, Table 5-1, Table C-4, Table C-5, Table C-6, and Table C-13

Updated Features section

Updated Unsupported Features section.

Updated Requirements section

Updated SDK instances to Vitis software platform

Updated Vivado menu commands

07/30/2019

2.0

Updated Figure C-2 and Figure C-4

Updated Component Name section

Updated Table 2-8, Table C-2, Table C-3, and Table C-13

Added Figure 5-32

12/05/2018

2.0

Updated UHD-SDI Audio Extract Use Case section

Updated ZCU106 SMPTE UHD-SDI Audio-Video Pass-Through Example Design section

Updated Table 5-2 and HD-SDI TXOUTCLK frequencies

Added UHD-SDI GT Ports section

Added RX_ST352_DATA_DS<n> registers for C stream

04/04/2018

2.0

Added ZCU106 UHD-SDI Audio-Video Pass-Through Example Design

Added KCU116 UHD-SDI Audio-Video Loopback Example Design

Added Appendix C for UHD-SDI IP

Added Appendix D for Audio Test Pattern Generator IP

10/04/2017

1.0

Initial Xilinx release.