Running the Design on the Hardware - 2.0 English

SMPTE UHD-SDI Receiver Subsystem Product Guide

Document ID
PG290
Release Date
2022-04-26
Version
2.0 English

Use the following steps to run the BIT and ELF files on the hardware setup:

1. Connect the JTAG cable and USB-UART cable to the board.

2. Switch on the Board.

3. Open the board user interface GUI for Versal. The Enter Board Information tab opens, as shown in This Figure .

Figure 5-50: Enter Board Information

X-Ref Target - Figure 5-50

enter_board_info.PNG

4. Fill in the information as per the board part used, and then click OK . This displays a new tab.

5. Click on the Clock tab, and then set the user1 FMC1 si570 frequency clock to 148.35 as shown in This Figure below:

Figure 5-51: Setting the Clock Frequency

X-Ref Target - Figure 5-51

clock_info.PNG

6. Select the VCCAUX Workaround tab, and then select the checkbox for VCC_RAM (.78v) as shown in This Figure .

Figure 5-52: Setting VCC_RAM

X-Ref Target - Figure 5-52

VccAux.PNG

7. Scroll to and select the FMC tab.

8. Select the checkbox for Set Vadj (0.5 to 1.5V) , and then enter a voltage value in the 0.5-1.5V range, as shown in This Figure .

Figure 5-53: Setting the VADJ Value

X-Ref Target - Figure 5-53

FMC.PNG

9. Once the settings are passed, close the tabs.

10. Navigate to <Component Name>_ex/imports .

11. Start the Xilinx Software Debugger (XSDB) by using the command prompt to source XSDB from the build area.

12. Run the following command to program FPGA and to execute the application:

source xsdb.tcl

13. To observe the results:

a. Make sure that the UART cable is connected to the board and the PC.

b. Open Tera Term or PuTTY and configure the serial port (Interface 0) to 115200 baud with the default configuration. The UART console then displays SDI stream details on the console.