SDI Video Pass-through - 2.0 English

SMPTE UHD-SDI Receiver Subsystem Product Guide

Document ID
PG290
Release Date
2022-04-26
Version
2.0 English

The SMPTE UHD-SDI RX Subsystem receives and processes video or image data with audio.

The Xilinx® Versal GTY transceiver (RX) recovers the clock and feeds to the PICXO IP for jitter attenuation.

The jitter-attenuated clock is used as a reference clock by the GTY transceiver for the TX data path.

The UHDSDI GT Bridge IP passes data and control information between the GTY transceiver and UHDSDI RX and TX subsystem.

An AXI4-Stream FIFO is used for synchronization and temporary storage between the SMPTE UHD-SDI RX Subsystem and the SMPTE UHD-SDI TX Subsystem.

The SMPTE UHD-SDI TX Subsystem transmits SDI data from the AXI4-Stream FIFO after the application programs the SMPTE UHD-SDI TX Subsystem sub-core registers, based on the received SDI stream and ST-352 payload packet data.