SMPTE UHD-SDI RX Registers - 2.0 English

SMPTE UHD-SDI Receiver Subsystem Product Guide

Document ID
PG290
Release Date
2022-04-26
Version
2.0 English

The SMPTE UHD-SDI RX registers are available when the AXI4-Lite Interface is selected in the Vivado IDE. The SMPTE UHD-SDI RX IP core register space is shown in Table: SMPTE UHD-SDI RX IP Core Register Space .

IMPORTANT: This memory space must be aligned to an AXI word (32-bit) boundary.

All registers are in little endian format as shown in This Figure .

Figure 2-1: 32-bit Little Endian Example

X-Ref Target - Figure 2-1

X21289--pg290-endian.jpg
Table 2-13: SMPTE UHD-SDI RX IP Core Register Space

Offset

Name

Width

Access

Description

0x00

RST_CTRL

32-bit

R/W

Enable and soft reset controls for the IP core

0x04

MODULE_CTRL

32-bit

R/W

Module control register

0x08

RESERVED

32-bit

N/A

N/A

0x0C

GLBL_IER

32-bit

R/W

Global interrupt enable register

0x10

ISR

32-bit

R/W1C

Interrupt status register

0x14

IER

32-bit

R/W

Interrupt enable register

0x18

RX_ST352_VALID

32-bit

RO

ST352 packet valid indication

0x1C

RX_ST352_DATA_DS1

32-bit

RO

Data stream 1 ST352 packet data

0x20

RX_ST352_DATA_DS3

32-bit

RO

Data stream 3 ST352 packet data

0x24

RX_ST352_DATA_DS5

32-bit

RO

Data stream 5 ST352 packet data

0x28

RX_ST352_DATA_DS7

32-bit

RO

Data stream 7 ST352 packet data

0x2C

RX_ST352_DATA_DS9

32-bit

RO

Data stream 9 ST352 packet data

0x30

RX_ST352_DATA_DS11

32-bit

RO

Data stream 11 ST352 packet data

0x34

RX_ST352_DATA_DS13

32-bit

RO

Data stream 13 ST352 packet data

0x38

RX_ST352_DATA_DS15

32-bit

RO

Data stream 15 ST352 packet data

0x3C

VERSION

32-bit

RO

Version Register

0x40

SS_CONFIG

32-bit

RO

IP core Configuration

0x44

MODE_DET_STS

32-bit

RO

Mode detect status

0x48

TS_DET_STS

32-bit

RO

Transport Stream detect status

0x4C

RX_EDH_STS

32-bit

RO

EDH check status

0x50

RX_EDH_ERRCNT_EN

32-bit

R/W

Enable EDH error count

0x54

RX_EDH_ERRCNT

32-bit

RO

RX EDH error count

0x58

RX_CRC_ERR

32-bit

RO

RX CRC error indication

0x5C

VIDEO_LOCK_WINDOW

32-bit

R/W

Video lock window

0x60

RESERVED

32-bit

N/A

N/A

0x64

RESERVED

32-bit

N/A

N/A

0x68

RESERVED

32-bit

N/A

N/A

0x6C

RESERVED

32-bit

N/A

N/A

0x70

RX_ST352_DATA_DS2

32-bit

RO

Data stream 2 ST352 packet data

0x74

RX_ST352_DATA_DS4

32-bit

RO

Data stream 4 ST352 packet data

0x78

RX_ST352_DATA_DS6

32-bit

RO

Data stream 6 ST352 packet data

0x7C

RX_ST352_DATA_DS8

32-bit

RO

Data stream 8 ST352 packet data

0x80

RX_ST352_DATA_DS10

32-bit

RO

Data stream 10 ST352 packet data

0x84

RX_ST352_DATA_DS12

32-bit

RO

Data stream 12 ST352 packet data

0x88

RX_ST352_DATA_DS14

32-bit

RO

Data stream 14 ST352 packet data

0x8C

RX_ST352_DATA_DS16

32-bit

RO

Data stream 16 ST352 packet data

Notes:

1. Access type and reset value for all the reserved bits in the registers is read-only with value 0.

2. Register accesses should be word aligned and there is no support for a write strobe. WSTRB is not used internally.

3. Only the lower 7 bits (6:0) of the read and write address of the AXI4-Lite interface are decoded. This means that accessing address 0x00 and 0x80 results in reading the same address of 0x00.

4. Reads and writes to addresses outside this table do not return an error.