Video or image data with audio is received and processed by the SMPTE UHD-SDI RX Subsystem. The clock is recovered by the Xilinx® UltraScale™+ GTH transceiver (RX) and fed to the on-board PLL for jitter attenuation. A jitter-attenuated clock is used as a reference clock by the GTH transceiver for the TX data path. An AXI4-Stream FIFO is used for synchronization and temporary storage between the SMPTE UHD-SDI RX Subsystem and the UHD-SDI TX Subsystem. The UHD-SDI TX Subsystem transmits SDI data from the AXI4-Stream FIFO after the application programs the UHD-SDI TX Subsystem sub-core registers based on the received SDI stream and the ST-352 payload packet data.