The UHD-SDI pass-through example design, shown in This Figure , is built using the SMPTE UHD-SDI TX and RX subsystems. Video or image data is received and processed by the SMPTE UHD-SDI RX Subsystem. The clock is recovered by the Xilinx® UltraScale™+ GTH transceiver (RX) and fed to the on-board PLL for jitter attenuation. A jitter-attenuated clock is used as a reference clock by the GTH transceiver for the TX data path. An AXI4-Stream FIFO is used for synchronization and temporary storage between the SMPTE UHD-SDI RX Subsystem and the SMPTE UHD-SDI TX Subsystem. The SMPTE UHD-SDI TX Subsystem transmits SDI data from the AXI4-Stream FIFO after the application programs the SMPTE UHD-SDI TX Subsystem sub-core registers based on the received SDI stream and ST-352 payload packet data. The example design application software runs on the Zynq UltraScale+ MPSoC Arm processor subsystem (PS) and is fully software controlled.
Note: The Zynq UltraScale+ MPSoC PS is not shown in This Figure for simplicity.