The clocking architecture for the Low Latency 10/25G MAC with PCS/PMA clocking is illustrated in the following figure. Low latency is achieved by omitting the RX FIFOs, which results in a different clocking arrangement. There are two clock domains in the datapath, as illustrated by the dashed lines in the following figure.
- refclk_p0, refclk_n0, tx_serdes_refclk
refclkdifferential pair is required to be an input to the FPGA. The example design includes a buffer to convert this clock to a single-ended signal
refclk, which is used as the reference clock for the GT block. The
tx_serdes_refclkis directly derived from
refclk. Note that
refclkmust be chosen so that the
tx_serdes_refclkmeets the requirements of 802.3, which is within 100 ppm of 390.625 MHz for 25G, and 156.25 MHz for 10G.
- This clock is used for clocking data into the TX AXI4-Stream Interface and it is also the reference clock for the
TX control and status signals. It is the same frequency as
tx_serdes_refclk. Because there is no TX FIFO, you must respond immediately to the
rx_clk_outoutput signal is presented as a reference for the RX control and status signals processed by the RX core. It is the same frequency as the
rx_serdes_clk. Because there is no RX FIFO, this is also the clock which drives the RX AXI4-Stream Interface. In this arrangement,
tx_clk_outare different frequencies and have no defined phase relationship to each other.
dclksignal must be a convenient stable clock. It is used as a reference frequency for the GT helper blocks which initiate the GT itself. In the example design, a typical value is 75 MHz, which is readily derived from the 300 MHz clock available on the VCU107 evaluation board. Note that the actual frequency must be known to the GT helper blocks for proper operation.