AXI4-Stream Control and Status Ports - 2.7 English

1G/10G/25G Switching Ethernet Subsystem Product Guide (PG292)

Document ID
PG292
Release Date
2022-05-11
Version
2.7 English
Table 1. AXI4-Stream Interface – TX Path Control/Status Signals
Name I/O Description Clock Domain
ctl_tx_custom_preamble_enable 1 I When asserted, this signals enables the use of tx_preamblein as a custom preamble instead of inserting a standard preamble.
Note: When the core is switched to 1G, this should always be 0.
tx_clk_out
tx_preamblein [55:0] 1 I

This is the custom preamble which is a separate input port rather than being in-line with the data.

It should be valid during the start of packet.

Note: When the core is switched to 1G, this should always be 0. This port is available for non-Versal device only.
tx_clk_out
ctl_tx_ipg_value[3:0] 1 I This signal can be optionally present. The ctl_tx_ipg_value defines the target average minimum Inter Packet Gap (IPG, in bytes) inserted between AXI4-Stream packets. Valid values are 8 to 12. The ctl_tx_ipg_value can be programmed to a value in the 0 to 7 range, but in that case, it is interpreted as 8 (the minimum valid value).
Note: When the core is switched to 1G, this should always be 12.
tx_clk_out
ctl_tx_enable I TX Enable. This signal is used to enable the transmission of data when it is sampled as a 1. When sampled as a 0, only idles are transmitted by the core. This input should not be set to 1 until the receiver it is sending data to (that is, the receiver in the other device) is fully synchronized and ready to receive data (that is, the other device is not sending a remote fault condition). Otherwise, loss of data can occur. If this signal is set to 0 while a packet is being transmitted, the current packet transmission is completed and then the core stops transmitting any more packets. tx_clk_out
ctl_tx_send_rfi 2 I Transmit Remote Fault Indication (RFI) code word. If this input is sampled as a 1, the TX path only transmits Remote Fault code words. This input should be set to 1 until the RX path is fully synchronized and is ready to accept data from the link partner. tx_clk_out
ctl_tx_send_lfi 2 I Transmit Local Fault Indication (LFI) code word. Takes precedence over Remote Fault Indication (RFI). tx_clk_out
ctl_tx_send_idle I Transmit Idle code words. If this input is sampled as a 1, the TX path only transmits Idle code words. This input should be set to 1 when the partner device is sending RFI code words. tx_clk_out
ctl_tx_fcs_ins_enable I Enable FCS insertion by the TX core. If this bit is set to 0, the core does not add FCS to packet. If this bit is set to 1, the core calculates and adds the FCS to the packet. This input cannot be changed dynamically between packets. tx_clk_out
ctl_tx_ignore_fcs I Enable FCS error checking at the AXI4-Stream interface by the TX core. This input only has effect when ctl_tx_fcs_ins_enable is Low. If this input is Low and a packet with bad FCS is being transmitted, it is not binned as good. If this input is High, a packet with bad FCS is binned as good.

The error is flagged on the signals stat_tx_bad_fcs and stomped_fcs, and the packet is transmitted as it was received.

Note: Statistics are reported as if there was no FCS error.
tx_clk_out
stat_tx_local_fault 2 O A value of 1 indicates the transmit decoder state machine is in the TX_INIT state. The output is level-sensitive. tx_clk_out
  1. This signal is valid for 64-bit core configurations only.
  2. This signal is not valid in 1G mode.
Table 2. AXI4-Stream Interface – RX Path Control/Status Signals
Name I/O Description Clock Domain
rx_preambleout [55:0] 2 O This is the preamble, and now a separate output instead of inline with data as was done with previous releases.
Note: When the core is switched to 1G, this should always be 0. This port is available for non-Versal device only.
rx_core_clk
ctl_rx_enable I RX Enable. For normal operation, this input must be set to 1. When this input is set the to 0, after the RX completes the reception of the current packet (if any), it stops receiving packets by keeping the PCS from decoding incoming data. In this mode, there are no statistics reported and the AXI4-Stream interface is idle. rx_clk_out
ctl_rx_check_preamble 2 I When asserted, this input causes the MAC to check the preamble of the received frame. rx_clk_out
ctl_rx_check_sfd 1 I When asserted, this input causes the MAC to check the Start of Frame Delimiter of the received frame. rx_clk_out
ctl_rx_force_resync 1 I RX force resynchronization input. This signal is used to force the RX path to reset and re-synchronize. A value of 1 forces the reset operation. A value of 0 allows normal operation. Note that this input should normally be Low and should only be pulsed (1 cycle minimum pulse). rx_clk_out
ctl_rx_delete_fcs I Enable FCS removal by the RX core. If this bit is set to 0, the core does not remove the FCS of the incoming packet. If this bit is set to 1, the core deletes the FCS to the received packet. Note that FCS is not deleted for packets that are less than or equal to 8 bytes long. This input should only be changed while the corresponding reset input is asserted. rx_clk_out
ctl_rx_ignore_fcs I Enable FCS error checking at the AXI4-Stream interface by the RX core. If this bit is set to 0, a packet received with an FCS error is sent with the rx_axis_tuser pin asserted during the last transfer (rx_axis_tuser and rx_axis_tlast sampled as 1). If this bit is set to 1, the core does not flag an FCS error at the AXI4-Stream interface.
Note: The statistics are reported as if the packet is good. The signal stat_rx_bad_fcs, however, reports the error.
rx_clk_out
ctl_rx_max_packet_len[14:0] I Any packet longer than this value is considered to be oversized. If a packet has a size greater than this value, the packet is truncated to this value and the rx_axis_tuser signal is asserted along with the rx_axis_tlast signal. Packets less than 4 bytes are dropped.

ctl_rx_max_packet_len[14] is reserved and must be set to 0.

rx_clk_out
ctl_rx_min_packet_len[7:0] I

Any packet shorter than this value is considered to be undersized. If a packet has a size less than this value, the rx_axis_tuser signal is asserted during the rx_axis_tlast asserted cycle. Packets less than 4 bytes are dropped.

The ctl_rx_min_packet_len[7:0] value should be >=64B.

rx_clk_out
stat_rx_framing_err[1:0] 1 O The RX sync header bits framing error is a bus that indicates how many sync header errors were received. The value of the bus is only valid when stat_rx_framing_err_valid is a 1. The values can be updated at any time and are intended to be used as increment values for sync header error counters. rx_clk_out
stat_rx_framing_err_valid 1 O Valid indicator for stat_rx_framing_err. When sampled as a 1, the value on stat_rx_framing_err is valid. rx_clk_out
stat_rx_local_fault 1 O This output is High when stat_rx_internal_local_fault or stat_rx_received_local_fault is asserted. This output is level sensitive. rx_clk_out
stat_rx_status O Indicates current status of the link. rx_clk_out
stat_rx_block_lock 1 O Block lock status. A value of 1 indicates that block lock is achieved as defined in Clause 49.2.14 and MDIO register 3.32.0 This output is level sensitive. rx_clk_out
stat_rx_remote_fault 1 O Remote fault indication status. If this bit is sampled as a 1, it indicates a remote fault condition was detected. If this bit is sampled as a 0, remote fault condition does not exist. This output is level sensitive. rx_clk_out
stat_rx_bad_fcs[1:0] O Bad FCS indicator. The value on this bus indicates packets received with a bad FCS, but not a stomped FCS during a cycle. A stomped FCS is defined as the bitwise inverse of the expected good FCS. This output is pulsed for one clock cycle to indicate an error condition. Note that pulses can occur in back-to-back cycles. rx_clk_out
stat_rx_stomped_fcs[1:0] O Stomped FCS indicator. The value on this bus indicates the packets were received with a stomped FCS. A stomped FCS is defined as the bitwise inverse of the expected good FCS. This output is pulsed for one clock cycle to indicate the stomped condition. Note that pulses can occur in back to back cycles. rx_clk_out
stat_rx_truncated O Packet truncation indicator. A value of 1 indicates that the current packet in flight is truncated due to its length exceeding ctl_rx_max_packet_len[14:0]. This output is pulsed for one clock cycle to indicate the truncated condition. Note that pulses can occur in back to back cycles. rx_clk_out
stat_rx_internal_local_fault 1 O High when an internal local fault is generated due to any one of the following: test pattern generation or high bit error rate. Note that this signal remains High as long as the fault condition persists.
Note: For the 64-bit variant, when FEC is enabled or when preemption is disabled, this signal will be tied to 0 internally.
rx_clk_out
stat_rx_received_local_fault 1 O High when enough local fault words are received from the link partner to trigger a fault condition as specified by the IEEE fault state machine. Remains High as long as the fault condition persists.
Note: For the 64-bit variant, when FEC is enabled or when preemption is disabled, this signal will be tied to 0 internally.
rx_clk_out
stat_rx_hi_ber 1 O High Bit Error Rate (BER) indicator. When set to 1, the BER is too high as defined by IEEE Std. 802.3. Corresponds to MDIO register bit 3.32.1 as defined in Clause 49.2.14. This output is level sensitive. rx_clk_out
ctl_rx_custom_preamble_enable 2 I When asserted, this signal causes the side band of a packet presented on the AXI4-Stream to be the preamble as it appears on the line.
Note: When the core is switched to 1G, this should always be 0.
rx_clk_out
  1. This signal is not valid in 1G mode.
  2. This signal is valid for 64-bit core configurations only.