AXI4-Stream User Interface Signals - 2.7 English

1G/10G/25G Switching Ethernet Subsystem Product Guide (PG292)

Document ID
PG292
Release Date
2022-05-11
Version
2.7 English

Ports in this section are available when Ethernet MAC+PCS/PMA-32 bit is selected from the Configuration tab.

Table 1. AXI4-Stream User Interface Signals
Name Size I/O Description
tx_unfout_* 1 O

Underflow signal for TX datapath from core. If tx_unfout_* is sampled as 1, a violation has occurred meaning the current packet is corrupted. Error control blocks are transmitted as long as the underflow condition persists.

It is up to the user logic to ensure a complete packet is input to the core without under-running the TX datapath interface.

Note: When this signal sampled as 1, you must apply tx_reset/sys_reset to recover the subsystem from the underflow issue. tx_reset resets the TX path only and sys_reset recovers the complete system.
tx_axis_tready_* 1 O TX path ready signal from core.
tx_axis_tvalid_* 1 I Transmit AXI4-Stream Data valid.
tx_axis_tdata_* 32 I Transmit AXI4-Stream Data bus.
tx_axis_tlast_* 1 I Transmit AXI4-Stream tlast.
tx_axis_tkeep_* 8/4 I Transmit AXI4-Stream tkeep.
tx_axis_tuser_* 1 I Transmit AXI4-Stream tuser.
tx_preamblein_* 56 I Transmit AXI4-Stream preamble.
rx_axis_tvalid_* 1 O Receive AXI4-Stream Data valid.
rx_axis_tdata_* 32 O Receive AXI4-Stream Data bus.
rx_axis_tlast_* 1 I Receive AXI4-Stream tlast.
rx_axis_tkeep_* 8/4 I Receive AXI4-Stream tkeep.
rx_axis_tuser_* 1 I Receive AXI4-Stream tuser.
rx_preamblein_* 56 I Receive AXI4-Stream preamble.