Auto-Negotiation Ports - 2.7 English

1G/10G/25G Switching Ethernet Subsystem Product Guide (PG292)

Document ID
PG292
Release Date
2022-05-11
Version
2.7 English

The following table shows the additional ports used for Auto-Negotiation. These signals are found at the *wrapper.v hierarchy file.

Table 1. Additional Ports for Auto-Negotiation
Port Name I/O Description Clock Domain
an_clk I Input Clock for the auto-negotiation circuit. The required frequency is indicated in the readme file for the release. It should be a free running clock.
Note: This port is not accessible to you. This is tied to dclk, which is a free-running clock.
Refer to Clocking.
an_reset I Asynchronous active-High reset. Async
ctl_autoneg_enable I Enable signal for auto-negotiation. an_clk
ctl_autoneg_bypass I Input to disable auto-negotiation and bypass the auto-negotiation function. If this input is asserted, then auto-negotiation is turned off, but the PCS is connected to the outputs to allow operation. an_clk
ctl_an_nonce_seed[7:0] I

8-bit seed to initialize the nonce field Polynomial generator.

This input should always be set to a unique non-zero value for every instance of the auto-negotiator.

an_clk
ctl_an_pseudo_sel I Selects the polynomial generator for the bit 49 random BitGenerator. If this input is 1, then the polynomial is x7+x6+1. If this input is zero, then the polynomial is x7+x3+1. an_clk
ctl_restart_negotiation I This input is used to trigger a restart of the auto-negotiation, regardless of what state the circuit is currently in. an_clk
ctl_an_local_fault I This input signal is used to set the remote_fault bit of the transmit link codeword. an_clk
Signals Used for Pause Ability Advertising
ctl_an_pause I This input signal is used to set the PAUSE bit, (C0), of the transmit link codeword. This signal might not be present if the core does not support pause. an_clk
ctl_an_asmdir I This input signal is used to set the ASMDIR bit, (C1), of the transmit link codeword. This signal might not be present if the core does not support pause. an_clk
Ability Signal Inputs
ctl_an_ability_1000base_kx I These inputs identify the Ethernet protocol abilities that is advertised in the transmit link codeword to the link partner. A value of 1 indicates that the interface advertises that it supports the protocol. an_clk
ctl_an_ability_100gbase_cr10 I an_clk
ctl_an_ability_100gbase_cr4 I an_clk
ctl_an_ability_100gbase_kp4 I an_clk
ctl_an_ability_100gbase_kr4 I an_clk
ctl_an_ability_10gbase_kr I an_clk
ctl_an_ability_10gbase_kx4 I an_clk
ctl_an_ability_25gbase_cr I an_clk
ctl_an_ability_25gbase_cr1 I an_clk
ctl_an_ability_25gbase_kr I an_clk
ctl_an_ability_25gbase_kr1 I an_clk
ctl_an_ability_40gbase_cr4 I an_clk
ctl_an_ability_40gbase_kr4 I an_clk
ctl_an_ability_50gbase_cr2 I an_clk
ctl_an_ability_50gbase_kr2 I an_clk
ctl_an_fec_request I Used to control the clause 74 FEC request bit in the transmit link codeword. This signal might not be present if the IP core does not support clause 74 FEC. an_clk
ctl_an_fec_ability_override I Used to control the clause 74 FEC ability bit in the transmit link codeword. If this input is set, then the FEC ability bit in the transmit link codeword is cleared. This signal might not be present if the IP core does not support clause 74 FEC. an_clk
ctl_an_cl91_fec_ability I This bit is used to indicate clause 91 FEC ability. an_clk
ctl_an_cl91_fec_request I This bit is used to request clause 91 FEC. an_clk
stat_an_link_cntl_1000base_kx[1:0] O
Link Control outputs from the auto-negotiation controller for the various Ethernet protocols. Settings are as follows:
  • 00: DISABLE; PCS is disconnected
  • 01: SCAN_FOR_CARRIER; RX is connected to PCS
  • 11: ENABLE; PCS is connected for mission mode operation
  • 10: not used
an_clk
stat_an_link_cntl_100gbase_cr10[1:0] O an_clk
stat_an_link_cntl_100gbase_cr4[1:0] O an_clk
stat_an_link_cntl_100gbase_kp4[1:0] O an_clk
stat_an_link_cntl_100gbase_kr4[1:0] O an_clk
stat_an_link_cntl_10gbase_kr[1:0] O an_clk
stat_an_link_cntl_10gbase_kx4[1:0] O an_clk
stat_an_link_cntl_25gbase_cr[1:0] O an_clk
stat_an_link_cntl_25gbase_cr1[1:0] O an_clk
stat_an_link_cntl_25gbase_kr[1:0] O an_clk
stat_an_link_cntl_25gbase_kr1[1:0] O an_clk
stat_an_link_cntl_40gbase_cr4[1:0] O an_clk
stat_an_link_cntl_40gbase_kr4[1:0] O an_clk
stat_an_link_cntl_50gbase_cr2[1:0] O an_clk
stat_an_link_cntl_50gbase_kr2[1:0] O an_clk
stat_an_fec_enable O Used to enable the use of clause 74 FEC on the link. an_clk
stat_an_rs_fec_enable O Used to enable the use of clause 91 FEC on the link. an_clk
stat_an_tx_pause_enable O Used to enable station-to-station (global) pause packet generation in the transmit path to control data flow in the receive path. an_clk
stat_an_rx_pause_enable O Used to enable station-to-station (global) pause packet interpretation in the receive path, to control data flow from the transmitter. an_clk
stat_an_autoneg_complete O Indicates the auto-negotiation is complete and RX link status from the PCS has been received. an_clk
stat_an_parallel_detection_fault O Indicated a parallel detection fault during auto-negotiation. an_clk
stat_an_lp_ability_1000base_kx O These signals indicate the advertised protocol from the link partner. They all become valid when the output signal stat_AN_lp_Ability_Valid is asserted. A value of 1 indicates that the protocol is advertised as supported by the link partner. an_clk
stat_an_lp_ability_100gbase_cr10 O an_clk
stat_an_lp_ability_100gbase_cr4 O an_clk
stat_an_lp_ability_100gbase_kp4 O an_clk
stat_an_lp_ability_100gbase_kr4 O an_clk
stat_an_lp_ability_10gbase_kr O an_clk
stat_an_lp_ability_10gbase_kx4 O an_clk
stat_an_lp_ability_25gbase_cr O an_clk
stat_an_lp_ability_25gbase_kr O an_clk
stat_an_lp_ability_40gbase_cr4 O an_clk
stat_an_lp_ability_40gbase_kr4 O an_clk
stat_an_lp_ability_25gbase_cr1 O Indicates the advertised protocol from the link partner. Becomes valid when the output signal stat_AN_lp_Extended_Ability_Valid is asserted. A value of 1 indicates that the protocol is advertised as supported by the link partner. an_clk
stat_an_lp_ability_25gbase_kr1 O Indicates the advertised protocol from the link partner. Becomes valid when the output signal stat_AN_lp_Extended_Ability_Valid is asserted. A value of 1 indicates that the protocol is advertised as supported by the link partner. an_clk
stat_an_lp_ability_50gbase_cr2 O Indicates the advertised protocol from the link partner. Becomes valid when the output signal stat_AN_lp_Extended_Ability_Valid is asserted. A value of 1 indicates that the protocol is advertised as supported by the link partner. an_clk
stat_an_lp_ability_50gbase_kr2 O Indicates the advertised protocol from the link partner. Becomes valid when the output signal stat_AN_lp_Extended_Ability_Valid is asserted. A value of 1 indicates that the protocol is advertised as supported by the link partner. an_clk
stat_an_lp_pause O This signal indicates the advertised value of the PAUSE bit, (C0), in the receive link codeword from the link partner. It becomes valid when the output signal stat_AN_lp_Ability_Valid is asserted. an_clk
stat_an_lp_asm_dir O This signal indicates the advertised value of the ASMDIR bit, (C1), in the receive link codeword from the link partner. It becomes valid when the output signal stat_AN_lp_Ability_Valid is asserted. an_clk
stat_an_lp_fec_ability O This signal indicates the advertised value of the FEC ability bit in the receive link codeword from the link partner. It becomes valid when the output signal stat_AN_lp_Ability_Valid is asserted. an_clk
stat_an_lp_fec_request O This signal indicates the advertised value of the FEC Request bit in the receive link codeword from the link partner. It becomes valid when the output signal stat_AN_lp_Ability_Valid is asserted. an_clk
stat_an_lp_autoneg_able O This output signal indicates that the link partner is able to perform auto-negotiation. It becomes valid when the output signal stat_AN_lp_Ability_Valid is asserted. an_clk
stat_an_lp_ability_valid O This signal indicates when all of the link partner advertisements become valid. an_clk
an_loc_np_data[47:0] I Local Next Page codeword. This is the 48-bit codeword used if the loc_np input is set. In this data field, the bits NP, ACK, and T, bit positions 15, 14, 12, and 11, are not transferred as part of the next page codeword. These bits are generated in the Auto-Negotiation Intellectual Property Core (ANIPC). However, the Message Protocol bit, MP, in bit position 13, is transferred. an_clk
an_lp_np_data[47:0] O Link Partner Next Page Data. This 48-bit word is driven by the ANIPC with the 48-bit next page codeword from the remote link partner. an_clk
ctl_an_loc_np I Local Next Page indicator. If this bit is 1, the ANIPC transfers the next page word at input loc_np_data to the remote link partner. If this bit is 0, the ANIPC does not initiate the next page protocol. If the link partner has next pages to send, and the loc_np bit is clear, the ANIPC transfers null message pages. an_clk
ctl_an_lp_np_ack I Link Partner Next Page Acknowledge. This is used to signal the ANIPC that the next page data from the remote link partner at output pin lp_np_data has been read by the local host. When this signal goes High, the ANIPC acknowledges reception of the next page codeword to the remote link partner and initiate transfer of the next codeword. During this time, the ANIPC will remove the lp_np signal until the new next page information is available. an_clk
stat_an_loc_np_ack O This signal is used to indicate to the local host that the local next page data, presented at input pin loc_np_data, has been taken. This signal pulses High for 1 clock period when the ANIPC samples the next page data on input pin loc_np_data. When the local host detects this signal High, it must replace the 48-bit next page codeword at input pin loc_np_data with the next 48-bit codeword to be sent. If the local host has no more next pages to send, it must clear the loc_np input. an_clk
stat_an_lp_np O Link Partner Next Page. This signal is used to indicate that there is a valid 48-bit next page codeword from the remote link partner at output pin lp_np_data. This signal is driven Low when the lp_np_ack input signal is driven High, indicating that the local host has read the next page data. It remains Low until the next codeword becomes available on the lp_np_data output pin, the lp_np output is driven High again. an_clk
stat_an_lp_ability_extended_fec[1:0] O This output indicates the extended FEC abilities as defined in Schedule 3. an_clk
stat_an_lp_extended_ability_valid O When this bit is 1, it indicates that the detected extended abilities are valid. an_clk
stat_an_lp_rf O This bit indicates link partner remote fault. an_clk
stat_an_start_tx_disable O When ctl_autoneg_enable is High and ctl_autoneg_bypass is Low, this signal, stat_an_start_tx_disable, cycles High for 1 clock cycle at the very start of the TX_DISABLE phase of auto-negotiation. That is, when auto-negotiation enters state TX_DISABLE, this output will cycle High for 1 clock period. It effectively signals the start of auto-negotiation. an_clk
stat_an_start_an_good_check O When ctl_autoneg_enable is High and ctl_autoneg_bypass is Low, this signal, stat_an_start_an_good_check, cycles High for 1 clock cycle at the very start of the AN_GOOD_CHECK phase of auto-negotiation. That is, when auto-negotiation enters the state AN_GOOD_CHECK, this output will cycle High for 1 clock period. It effectively signals the start of link training. However, if link training is not enabled, that is. if the input ctl_lt_training_enable is Low, the stat_an_start_an_good_check output effectively signals the start of mission-mode operation. an_clk