Configuration and Status Registers for 1G/2.5G Ethernet PCS/PMA - 2.7 English

1G/10G/25G Switching Ethernet Subsystem Product Guide (PG292)
Document ID
PG292
Release Date
2023-10-18
Version
2.7 English

AXI4-Lite support has been added in the 1G Ethernet PCS/PMA IP to assist you in programming the control and status registers. The addresses of the registers are word aligned for AXI4-Lite accesses. Strobing for data while accessing these registers is disabled.

Any read/write operations to given addresses lead to read/write operations to the corresponding 16-bit register as defined in 1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047).

The following vendor-specific registers have been added to the MDIO PCS Address space when configured for 1000BASE-X operation. See the 1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047).

For registers 0x0000-0x003C, see 1000BASE-X or 2500BASE-X Standard Without Optional Auto-Negotiation Table in 1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047).

Table 1. 1588 Control: Vendor Specific Register 19
Bits Default Value Access Description
15.4 N/A RO Reserved
3 1 RW Timestamp correction enable.
  • When 1, the RX timestamp is adjusted to compensate for enabled PHY fixed and variable latencies.
  • When 0, no adjustment is made to the timestamp.
2 1 RW Fixed RX PHY latency correction enable.
  • When 1, the RX timestamp is adjusted to compensate for fixed PHY latency by using the correction value specified in Table 2-30.
  • When 0, no adjustment is made to compensate for fixed known latencies.
1 0 RO Reserved
0 1 RW Variable RX transceiver latency correction enable.
  • When 1, the RX timestamp is adjusted to compensate for measurable variable transceiver latency (for 1000BASE-X this is the barrel shift position of the serial-to-parallel converter in the GTX transceiver PMA). This only varies when the subsystem is initialized following a power-on, reset, or recovery from loss of synchronization; it then remains constant for normal operation.
  • When 0, no adjustment is made to compensate for measurable variable known latencies.
Table 2. RX PHY Fixed Latency: Vendor Specific Register 20
Bits Default Value Access Description
15:0 0xC8 RW RX 1000BASE-X Fixed Delay in ns.

This value is initialized to the known RX latency from the serial wire input into the FPGA, through the transceiver fixed latency components prior to the timestamping position.
Table 3. RX PHY Variable Latency: Vendor Specific Register 21
Bits Default Value Access Description
15:0 N/A RO RX 1000BASE-X variable RX Delay in UI.

This value is measured within the subsystem following RX synchronization (for 1000BASE-X this is the barrel shift position of the serial-to-parallel converted in the transceiver PMA). This only varies when the subsystem is initialized following a power-on, reset, or recovery from loss of synchronization; it then remains constant for normal operation.

See 1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047) for information on Configuration Registers for 1G/2.5G Ethernet PCS-PMA.