Data Lane Mapping - RX - 2.7 English

1G/10G/25G Switching Ethernet Subsystem Product Guide (PG292)

Document ID
PG292
Release Date
2022-05-11
Version
2.7 English

For receive data rx_axis_tdata, the port is logically divided into lane 0 to lane 3 for the 32-bit interface or lane 0 to lane 7 for the 64-bit interface with the corresponding bit of the rx_axis_tkeep word signifying valid data on rx_axis_tdata.

Table 1. rx_axis_tdata Lanes - 32-bits
Lane/rx_axis_tkeep rx_axis_tdata[31:0] bits
0 7:0
1 15:8
2 23:16
3 31:24
Table 2. rx_axis_tkeep Lanes - 64-bits
Lane/ rx_axis_tkeep rx_axis_tdata Bits
0 7:0
1 15:8
2 23:16
3 31:24
4 39:32
5 47:40
6 55:48
7 63:56