Debugging Auto-Negotiation and Link Training - 2.7 English

1G/10G/25G Switching Ethernet Subsystem Product Guide (PG292)

Document ID
PG292
Release Date
2022-05-11
Version
2.7 English

Auto-Negotiation

To enable auto-negotiation:

  • ctl_autoneg_enable = 1
  • ctl_autoneg_bypass = 0

Set ctl_an_* to advertise desired auto-negotiation settings.

When using the control and status interface the example design ties off the ctl_an_* values to valid settings. If using the register interface see Board Testing Steps for Auto-Negotiation and Link Training Using AXI4-Lite Interface for the register sequence.

Link Training

To enable link training set ctl_lt_training_enable to 1.

  • The core does not actually do any training. It only provides the control protocol required by section 72.6.10. The training algorithm is a user responsibility.
  • The core does not monitor the RX eye nor does it send any presets, initializations, or coefficient control requests to the link partner TX. It is recommended to set ctl_lt_rx_trained to 1. Setting ctl_lt_rx_trained tells the link partner that your RX training is completed, and that you will not be sending any more presets, initializations, or coefficient changes.
  • The core does not adjust any of the GT TX amplitude or coefficient control settings in response to any training messages received from the link partner. The example design link training Place_Holder logic will indicate that maximum limits have been reached. This should allow link training to complete.

Nonce

nonce_seed must be set to a non-zero value.

  • If connecting two ports with same nonce seed on the same board, resets must be released at different times.
  • If the nonce_seed is changed, an an_reset is needed to load the new value. This includes changing nonce_seed using the AXI4-Lite registers.

Next Pages

If the link partner sends next page, ctl_an_loc_np_ack must be set High to acknowledge the next page and allow auto-negotiation to complete. This control signal can be set High after next page is received or tied always High.

Details on Stages and Status Signals

  1. At the start of auto-negotiation there is a TX disable state where no data is seen to ensure that the link is down on both sides. The stat_an_stat_tx_disable signal toggles for one cycle to indicate the start of this stage.
  2. Following the TX disable state, auto-negotiation information is exchanged. During this stage stat_an_rxcdrhold is held High. The stat_an_lp_autoneg_able and stat_an_lp_ability_valid signals will toggle High for one clock cycle to indicate when stat_an_lp* information is valid.
  3. The stat_an_start_an_good_check signal toggles High for one cycle at the start of link training. The stat_an_rxcdrhold signal is deasserted and gtwiz_reset_rx_datapath toggled. After link training starts there is a 500 ms timer for training and block lock/link up in mission mode/normal PCS operation to complete or auto-negotiation will restart. The stat_lt_frame_lock signal goes High and stat_lt_rx_sof toggles when the link training block has achieved frame synchronization. The stat_lt_rx_sof signal continues to toggle High for one clock duration at the training frame boundary.
  4. When link training completes the stat_lt_signal_detect signal asserts and indicates the start of normal PCS operation.
  5. The an_autoneg_complete signal goes High when block lock, synchronization and alignment (if multi-lane core), stat_rx_status and stat_rx_valid_ctrl_code (stat_rx_valid_ctrl_code is only applicable to single lane 10G/25G core) go High.
  6. The an_autoneg_complete signal must go High within the 500 ms timeout or auto-negotiation will restart. If stat_rx_status goes back Low at any time then auto-negotiation restarts.

Simulation and Loopback

Auto-Negotiation TX disable state takes 50 ms of simulation time to complete. Use SIM_SPEED_UP option without pre-compiled IP libraries to speed up the wait time. See AR 73518 for more information on turning off pre-compiled libraries.

Auto-negotiation will not complete in loopback because auto-negotiation requires that the nonce value received from the link partner must be different than the nonce value sent to the link partner.

Starting signal list to add to ILA for debug:

  • sys_reset
  • an_reset
  • ctl_an_*
  • ctl_lt_*
  • stat_an_start_tx_disable
  • stat_an_rxcdrhold
  • stat_an_lp_autoneg_able
  • stat_an_lp_ability_valid
  • stat_an_start_an_good_check
  • stat_lt_frame_lock
  • stat_lt_signal_detect
  • stat_lt_link_training
  • stat_lt_link_training_fail
  • stat_rx_block_lock
  • stat_rx_synced (only available on multi-lane cores)
  • stat_rx_aligned (only available on mult-lane cores)
  • stat_rx_valid_ctrl_code (only available on 10G/25G core)
  • stat_rx_status
  • stat_rx_bad_code
  • stat_rx_hi_ber

If using line rate that supports Clause 74 Firecode FEC:

  • stat_fec_inc_cant_correct_count
  • stat_fec_lock_error
  • stat_fec_rx_lock
  • stat_fec_inc_correct_count
  • ctl_an_fec_10g_request
  • ctl_fec_rx_enable
  • ctl_fec_tx_enable
  • stat_an_fec_enable
  • stat_an_lp_fec_10g_ability
  • stat_an_lp_fec_10g_request

If using line rate that supports RS-FEC:

  • ctl_tx_rsfec_enable
  • ctl_rx_rsfec_enable
  • stat_rx_rsfec_am_lock
  • stat_an_rs_fec_enable
Note: If the link partner sends next pages, the ctl_an_lo_np_ack signal must be set. This port can be tied High.