Ethernet Specific Checks - 2.7 English

1G/10G/25G Switching Ethernet Subsystem Product Guide (PG292)

Document ID
PG292
Release Date
2022-05-11
Version
2.7 English

A number of issues can commonly occur during the first hardware test of an 1G/10G/25G Switching Ethernet Subsystem. These should be checked as indicated below.

It is assumed that the 1G/10G/25G Ethernet Subsystem has already passed all simulation testing which is being implemented in hardware. This is a pre-requisite for any kind of hardware debug.

The usual sequence of debugging is to proceed in the following sequence:

  1. Clean up signal integrity.
  2. Ensure that the SerDes achieves clock data recovery (CDR) lock.
  3. Check that the 1G/10G/25G Ethernet Subsystem IP has achieved word sync.
  4. Proceed to Interface and Protocol debug.