Example Design Hierarchy (GT in Example Design) - 2.7 English

1G/10G/25G Switching Ethernet Subsystem Product Guide (PG292)

Document ID
PG292
Release Date
2022-05-11
Version
2.7 English

When the 1/10/25G Ethernet subsystem is added to the Vivado IP integrator, the Run Block Automation IP Core and GT (serial transceivers) get connected with some helper blocks as per the core configuration. There is a reset interface IP, internal to 1/10/25G Ethernet IP, used to release TX/RX mstreset to Versal device GT and check for TX/RX mstresetdone status and reset sequencing to GT.

Figure 1. Single Core with GT in Example Design Hierarchy
Figure 2. Single Core with GT in Example Design Hierarchy (Versal ACAP)

The previous figures show the instantiation of various modules and their hierarchy for a single core configuration of the ethernet_1_10_25g design when the GT (serial transceiver) is outside the IP Core, that is, in the example design. This hierarchical example design is delivered when you select the Include GT subcore in example design option from the GT Selection and Configuration tab.

The ethernet_1_10_25g_0_core_support.v module is present in the hierarchy when you select the Include GT subcore in example design option from the GT Selection and Configuration tab or the Include Shared Logic in example design option from the Shared Logic tab. This instantiates the ethernet_1_10_25g_0_sharedlogic_wrapper.v module and the ethernet_1_10_25g_0.v module for the Include Shared Logic in example design option.

The user interface available for MAC/PCS configuration and PCS configuration configurations is the same as mentioned in the Overview topic.

The ethernet_1_10_25g_0.v module instantiates the necessary the sync registers/retiming pipeline registers for the synchronization of data between the core and the GT.

The ethernet_1_10_25g_0_pkt_gen_mon module is used to generate the data packets for sanity testing. The packet generation and checking is controlled by a Finite State Machine (FSM) module. Description of optional modules are as follows:

ethernet_1_10_25g_0_sharedlogic_wrapper
This module is present in the example design when you select the Include GT subcore in example design option from the GT Selection and Configuration tab or Include Shared Logic in the Example Design from the Shared Logic tab. This module brings all modules that can be shared between multiple IP cores and designs outside the IP core.
ethernet_1_10_25g_0_gt_wrapper
This module is present in the example design when you select the Include GT subcore in example design option from the GT Selection and Configuration tab. This module is having instantiations of the GT along with various helper blocks. The clocking helper blocks are used to generate the required clock frequency for the core.

The following figure shows the instantiation of various modules and their hierarchy for the multiple core configuration of the ethernet_1_10_25g example design when the GT is in the example design for non-Versal devices.

Note: For Versal devices, due to the limitation of the GT wizard, only one core can be instantiated in a GT dual. Other GT duals need to be used for instantiating the second core. In a GT quad, a maximum two core configuration is possible.
Figure 3. Multiple Cores with GT in Example Design Hierarchy

For Versal devices, the gt_quad_base (GT Wizard for Versal device) is part of the example design only, and 1/10/25G Ethernet Subsystem IP and GT (serial transceiver) IP is connected in the block design using the IP integrator.