Frame Reception - 2.7 English

1G/10G/25G Switching Ethernet Subsystem Product Guide (PG292)

Document ID
PG292
Release Date
2022-05-11
Version
2.7 English

The ingress frame can be either preempt or express type. The core determines the type and puts the ingress frame on either the express AXI4-Stream interface or on the preempt AXI4-Stream interface respectively.

Express traffic will be continuous and because the core does not have any buffering mechanism on this interface, you must be ready to accept the express frame at any given time.

Due to the nature of the preempt traffic, the frame can arrive as a set of fragments which will be assembled by the core. There is an option of inserting a FIFO on the preempt interface during core generation. When this FIFO is inserted, all the fragments of the preempt frame will be buffered and only when the assembly process successfully completed, the frame will be made available on the AXI4-Stream interface. If FIFO is not inserted, the tvalid on the AXI4-Stream interface can pulsate in-between fragments. Core asserts tlast to indicate completion of the fragment tlast assembly process; if the assembly process is not successful, it asserts tuser along with.

The following figure shows how the preempt frame fragments are presented on the AXI4-Stream interface when the FIFO is not inserted.

Figure 1. Preempt Frame Fragments: When the FIFO Not Inserted

Table 1. Control and Status Ports
Name I/O Description Clock Domain
CONTROL
ctl_en_preempt I

When asserted, it allows preemption.

For the very first time it is asserted, it triggers Verification if ctl_disable_verify = 1'b0 and stat_tx_mm_verified[1:0] = 2’b00.

tx_clk_out
ctl_hold_request I If asserted, preempt traffic is withheld. tx_clk_out
ctl_disable_verify I If asserted, it inhibits the verification process. tx_clk_out
ctl_restart_verify I A 0-to-1 transition will trigger Verification if ctl_disable_verify = 1’b0. tx_clk_out
ctl_addfrag_size[1:0] I

Fragment size remaining to enable pre-emption:

2’b00 = 64-bytes

2’b01= 128-bytes

2’b10 = 192-bytes

2’b11 = 256-bytes

tx_clk_out
ctl_verify_time[7:0] I Verification time-out value in milliseconds. Integer range 1-128. Default is 1 ms. tx_clk_out
ctl_verify_limit[3:0] I Number of times core attempts Verification. Integer range 1-15. Default is 3. tx_clk_out
p_frame_len_0 I Indicates the length of the frame, in bytes, being presented at the TX Preempt AIX-S interface. Should be valid at preempt frame SOP. tx_clk_out
STATUS

stat_tx_mm_verify[1:0]

(No Counter)

O

Indicates verification status.

[0] – When asserted, indicates that verification is complete.

[1] – When asserted, indicates that verification is successful.

The value contained in this status vector is valid only when ctl_en_preempt = 1’b1 and ctl_disable_verify = 1’b0

tx_clk_out
stat_tx_mm_status O Asserted when a preemptable packet (initial fragment or complete packet) is transmitted. tx_clk_out
stat_tx_mm_fragment O Asserted when a continuation fragment of an preemptable packet is transmitted. tx_clk_out
stat_tx_mm_hold O Asserted when ctl_hold_request transitions from 1’b0 to 1’b1. tx_clk_out
stat_rx_mm_assembly_error O Asserted when errors are detected during fragment assembly. rx_core_clk
stat_rx_mm_frame_smd_error O Asserted when the frame fragment is rejected due to an incorrect SMD value or arriving with SMD-C when no frame is in progress. rx_core_clk
stat_rx_mm_frame_assembly_ok O Asserted when all the preemptable frame fragments have been assembled and presented. rx_core_clk
stat_rx_mm_fragment O Asserted when a fragment frame is received. rx_core_clk
rx_p_frm_drop_0 O Asserted by the packet assembly FIFO when it cannot continue with preempt fragment assembly because its full. When this happens all the fragments of the preempt frame received so far will be discarded. rx_core_clk
rx_p_frm_drop_count_0 O Count of number of such events. rx_core_clk
  1. Timestamp ports description for express and preempt interface is similar to 1588v2 ports description. For more details, see Port Descriptions.