The IEEE 1588v2 feature of the 1G/10G/25G Switching Ethernet Subsystem provides accurate timestamping of Ethernet frames at the hardware level for both the ingress and egress directions.
Timestamps are captured according to the input clock source above. However, it is required that this time source be in the same clock domain as the SerDes. This might require re-timing by an external circuit provided by the user.
All ingress frames receive a timestamp. You need to interpret the received frames and determine whether a particular frame contains PTP information (by means of its Ethertype) and if the timestamp needs to be retained or discarded. Egress frames are timestamped if they are tagged as PTP frames. The timestamps of egress frames are matched to their user-supplied tags.
Timestamps for incoming frames are presented at the user interface during the same clock cycle as the start of packet. You can then append the timestamp to the packet as required.
By definition, a timestamp is captured coincident with the passing of the SOP through the capture plane within the 1G/10G/25G Switching Ethernet Subsystem. This is shown in the following diagrams.