IEEE 802.3 Clause 108 RS-FEC Interface - 2.7 English

1G/10G/25G Switching Ethernet Subsystem Product Guide (PG292)

Document ID
PG292
Release Date
2022-05-11
Version
2.7 English

Ports under this section are available when IEEE Clause 108 (RS-FEC) is selected from the Configuration tab.

Table 1. IEEE Clause 108 (RS-FEC) Control/Status/Statistics Signals
Name Size I/O Description
ctl_rx_rsfec_enable_correction_* 1 I

The setting on this bit takes effect after rx_resetn has been asserted Low (~rx_serdes_reset). New value is sampled on first cycle on reset.

Equivalent to MDIO register 1.200.0

  • 0: Decoder performs error detection without error correction (see IEEE 802.3by section 91.5.3.3).
  • 1: Decoder also performs error correction.
ctl_rx_rsfec_enable_indication_* 1 I

The setting on this bit takes effect after rx_resetn has been asserted Low (~rx_serdes_reset). New value sampled on the first cycle on reset.

Equivalent to MDIO register 1.200.1

  • 0: Bypass the error indication function (see IEEE Std 802.3by section 91.5.3.3).
  • 1: Decoder indicates errors to the PCS sublayer.
ctl_rsfec_enable_* 1 I The setting on this bit takes effect after rx_resetn has been asserted Low (~rx_serdes_reset). New value is sampled on the first cycle on reset.

Enable RS-FEC function.

Note: Some variants of the 1G/10G/25G Subsystem can have individual RX and TX enable signals.
ctl_rsfec_ieee_error_indication_mode_* 1 I

The setting on this bit takes effect after rx_resetn has been asserted Low (~rx_serdes_reset). New value is sampled on the first cycle on reset.

  • 1: Core conforms to the IEEE RS-FEC specification.
  • 0: If ctl_rx_rsfec_enable_correction and ctl_rx_rsfec_enable_indication are set to zero, the RS decoder is bypassed.
ctl_rsfec_consortium_25g_* 1 I Switches between IEEE Clause 108 and 25G Ethernet Consortium mode.

The setting on this bit takes effect after rx_resetn has been asserted Low (~rx_serdes_reset). New value is sampled on the first cycle on reset.

  • 1 = 25G Consortium specification mode.
  • 0 = IEEE 802.3by mode.
Note: Some variants of the 1G/10G/25G Subsystem can have individual RX and TX consortium signals.
stat_rx_rsfec_hi_ser_* 1 O Set to one if the number of RS-FEC symbol errors in a window of 8192 codewords exceeds the threshold K = 417 and is set to zero otherwise.
stat_rx_rsfec_lane_alignment_status_* 1 O A value of 1 indicates that the RX RS-FEC block has achieved alignment on the data from the transceiver.
stat_rx_rsfec_corrected_cw_inc_* 1 O Increment for corrected errors.
stat_rx_rsfec_uncorrected_cw_inc_* 1 O Increment for uncorrected errors.
stat_rx_rsfec_err_count0_inc_* 3 O Increment for detected errors.
stat_tx_rsfec_lane_alignment_status_* 1 O A value of 1 indicates that the TX RS-FEC block has achieved alignment on the incoming PCS data.