IP Facts - 2.7 English

1G/10G/25G Switching Ethernet Subsystem Product Guide (PG292)

Document ID
PG292
Release Date
2022-05-11
Version
2.7 English
Facts Table
Subsystem Specifics
Supported Device Family 1 3

Versal® ™ ACAP

Zynq® UltraScale+™ RFSoC

Zynq® UltraScale+™ MPSoC

Virtex® UltraScale+™

Kintex® UltraScale+™

Virtex® UltraScale™ ™

Kintex UltraScale

Artix UltraScale+

Supported User Interfaces AXI4-Stream and AXI4-Lite for all variants

XGMII and GMII for PCS-only variants

Resources Performance and Resource Utilization web page
Provided with Subsystem
Design Files Encrypted register transfer level (RTL)
Example Design Verilog
Test Bench Verilog
Constraints File Xilinx Design Constraints (XDC)
Simulation Model Verilog
Supported S/W Driver N/A
Tested Design Flows 2
Design Entry Vivado Design Suite
Simulation For supported simulators, see the Xilinx Design Tools: Release Notes Guide.
Synthesis Vivado Synthesis
Support
Release Notes and Known Issues Master Answer Record: 75842
All Vivado IP Change Logs Master Vivado IP Change Logs: 72775
Xilinx Support web page
  1. For a complete list of supported devices, see the Vivado IP catalog.
  2. For the supported versions of third-party tools, see the Xilinx Design Tools: Release Notes Guide.
  3. UltraScale and UltraScale+ devices with a speed grade of -1,-1L,-1LV, -1H, or -1HV do not support 25G mode.