Include GT Subcore in Example Design Ports - 2.7 English

1G/10G/25G Switching Ethernet Subsystem Product Guide (PG292)

Document ID
PG292
Release Date
2022-05-11
Version
2.7 English

The following ports are available when the Include GT subcore in Example Design option is selected in the GT Selection and Configuration tab.

For the port descriptions, see the UltraScale Architecture GTY Transceivers User Guide (UG578) and the UltraScale Architecture GTH Transceivers User Guide (UG576).

Table 1. Include GT Subcore in Example Design Ports
Name Size I/O Description
gtwiz_txpllclksel_* 1 2 O -
gtwiz_rxpllclksel_* 1 2 O -
gtwiz_txsysclksel_* 1 2 O -
gtwiz_rxsysclksel_* 1 2 O -
gtwiz_rxoutclksel_* 1 3 O -
gtwiz_txoutclksel_* 1 3 O -
gtwiz_rxbufstatus_* 3 I -
gtwiz_txbufstatus_* 2 I -
gtwiz_userclk_tx_usrclk_out_* 1 I -
gtwiz_userclk_rx_usrclk_out_* 1 I -
gtwiz_userclk_tx_usrclk2_out_* 1 I -
gtwiz_userclk_rx_usrclk2_out_* 1 I -
gtwiz_buffbypass_tx_reset_* 1 1 O -
gtwiz_buffbypass_tx_start_user_* 1 1 O -
gtwiz_buffbypass_tx_done_* 1 1 I -
gtwiz_buffbypass_rx_reset_* 1 1 O -
gtwiz_buffbypass_rx_start_user_* 1 1 O -
gtwiz_txdiffctrl_* 4 O -
gtwiz_cplllock_* 1 I -
gtwiz_rxresetdone_* 1 I -
gtwiz_txresetdone_* 1 I -
gtwiz_rxclkcorcnt_* 2 I -
gtwiz_rxlpmen_* 1 O -
gtwiz_p_usrclk2_div_* 3 O -
gtwiz_rx8b10ben_* 1 O -
gtwiz_rxcommadeten_* 1 O -
gtwiz_rxdlybypass_* 1 1 O -
gtwiz_tx8b10ben_* 1 O -
gtwiz_rxmcommaalignen_* 1 O -
gtwiz_rxpcommaalignen_* 1 O -
gtwiz_rxphdlypd_* 1 O -
gtwiz_txdlybypass_* 1 1 O -
gtwiz_rplllock_* 2 1 I -
gtwiz_rpllpd_* 2 1 O -
gtwiz_rplllocken_* 2 1 O -
gtwiz_rpllreset_* 2 1 O -
gtwiz_txphdlypd_* 1 O -
gtwiz_txpippmpd_* 1 1 O -
gtwiz_txpippmsel_* 1 O -
gtwiz_txpostcursor_* 5 O -
gtwiz_cpllpd_* 1 O -
gtwiz_cplllocken_* 1 O -
gtwiz_rxpd_* 2 O -
gtwiz_txpd_* 2 O -
gtwiz_txelecidle_* 1 O -
gtwiz_reset_rx_done_* 1 I -
gtwiz_reset_tx_done_* 1 I -
gtwiz_txctrl0_* 16 O -
gtwiz_txctrl1_* 16 O -
gtwiz_txctrl2_* 8 O -
gtwiz_rxctrl0_* 16 I -
gtwiz_rxctrl1_* 16 I -
gtwiz_rxctrl2_* 8 I -
gtwiz_rxctrl3_* 8 O -
gtwiz_rxgearboxslip_* 1 O -
gtwiz_rxdatavalid_* 2 I -
gtwiz_rxheader_* 6 I -
gtwiz_rxheadervalid_* 2 I -
gtwiz_rx_serdes_data_* 128 I -
gtwiz_tx_serdes_data_* 128 O -
gtwiz_txheader_* 6 O -
gtwiz_txsequence_* 7 O -
gtwiz_rxpmaresetdone_* 1 I -
gtwiz_txpmaresetdone_* 1 I -
apb3clk_* 3 1 I -
apb3paddr_* 3 16 O -
apb3penable_* 3 1 O -
apb3prdata_* 3 32 I -
apb3pready_* 3 1 I -
apb3presetn_* 3 1 O -
apb3psel_* 3 1 O -
apb3pslverr_* 3 1 I -
apb3pwdata_* 3 32 O -
apb3pwrite_* 3 1 O -
gtwiz_buffbypass_rx_done_* 1 1 I -
gtwiz_cpllreset_* 1 O -
gt_reset_all_* 1 1 O Reset signal from the core to the GT.
gtwiz_drpdo_* 1 16 I DRP data signal from the GT to the core.
gtwiz_drprdy_* 1 1 I DRP ready signal from the GT to the core.
gtwiz_drpen_* 1 1 O The drpen signal from the core to the GT.
gtwiz_drpwe_* 1 1 O The drpwe signal from the core to the GT.
gtwiz_drpaddr_* 1 16 O The drpaddr signal from the core to the GT
gtwiz_drpdi_* 1 16 O DRP data signal from the core to the GT.
gt_drpdo_* 1 16 O DRP read data from GT to the user, using the DRP arbiter within the core.
gt_drprdy_* 1 1 O The drprdy signal from GT to the user, using the DRP arbiter within the core.
gt_drp_gnt_* 1 1 O DRP grant signal from the DRP arbiter to the user to enable the GT DRP read/write from the user side.
gt_drp_req_* 1 1 I DRP request from the user to the DRP arbiter to perform the GT read/write operation.
gt_drpen_* 1 1 I The drpen signal from the user to the DRP arbiter to perform the GT read/write operation.
gt_drpwe_* 1 1 I The drpwe signal from the user to the DRP arbiter to perform the GT read/write operation.
gt_drpaddr_* 1 10 I The drpaddr signal from the user to the DRP arbiter to perform the GT read/write operation.
gt_drpdi_* 1 16 I The drpdi signal from the user to the DRP arbiter to perform the GT read/write operation.
stat_tx_packet_1024_1518_bytes_* 1 O Increment for good and bad packets transmitted that contain 1,024 to 1,518 bytes.
stat_tx_packet_1519_1522_bytes_* 1 O Increment for good and bad packets transmitted that contain 1,519 to 1,522 bytes.
stat_tx_packet_1523_1548_bytes_* 1 O Increment for good and bad packets transmitted that contain 1,519 to 1,522 bytes.
stat_tx_packet_1549_2047_bytes_* 1 O Increment for good and bad packets transmitted that contain 1,523 to 1,548 bytes.
stat_tx_packet_2048_4095_bytes_* 1 O Increment for good and bad packets transmitted that contain 1,549 to 2,047 bytes.
stat_tx_packet_4096_8191_bytes_* 1 O Increment for good and bad packets transmitted that contain 4,096 to 8,191 bytes.
stat_tx_packet_8192_9215_bytes_* 1 O Increment for good and bad packets transmitted that contain 8,192 to 9,215 bytes.
stat_tx_packet_small_* 1 O Increment for all packets that are less than 64 bytes long. Packets that are less than 64 bytes are not transmitted.
stat_tx_packet_large_* 1 O Increment for all packets that are more than 9,215 bytes long.
stat_tx_frame_error_* 1 O Increment for packets with tx_errin set to indicate an EOP abort.
gig_ethernet_pcs_pma_status_vector_* 16 O See Status Vector table in 1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047).
gig_ethernet_pcs_pma_configuration_vector_* 5 O See Configuration Vector table in 1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047).
stat_core_speed_* 2 O Indicates the operating core speed:
  • 2'b10: Core configured in 10G mode.
  • 2'b01: Core configured in 1G mode.
  • 2'b00: Core configured in 25G mode.
gpcs_resetdone_* 1 O Indicates the 1G core is out of reset.
gt_switching_* 1 O

Indicates the GT DRP operation to switch the line rate is in progress.

  1. This port is available for non-Versal device only.
  2. This port is available for Versal device only.
  3. This port is available for Versal device only when timestamping is enabled.