Link Training Ports - 2.7 English

1G/10G/25G Switching Ethernet Subsystem Product Guide (PG292)

Document ID
PG292
Release Date
2022-05-11
Version
2.7 English

The following table shows the Link Training ports.

Table 1. Link Training Ports
Port Name I/O Description Clock Domain
ctl_lt_training_enable I Enables link training. When link training is disabled, all PCS lanes function in mission mode. tx_serdes_clk
ctl_lt_restart_training I This signal triggers a restart of link training regardless of the current state. tx_serdes_clk
ctl_lt_rx_trained I This signal is asserted to indicate that the receiver finite impulse response (FIR) filter coefficients have all been set, and that the receiver portion of training is complete. tx_serdes_clk

stat_lt_signal_detect

O This signal indicates when the respective link training state machine has entered the SEND_DATA state, in which normal PCS operation can resume. tx_serdes_clk

stat_lt_training

O This signal indicates when the respective link training state machine is performing link training. tx_serdes_clk

stat_lt_training_fail

O This signal is asserted during link training if the corresponding link training state machine detects a time-out during the training period. tx_serdes_clk

stat_lt_frame_lock

O When link training has begun, these signals are asserted, for each physical medium dependent (PMD) lane, when the corresponding link training receiver is able to establish a frame synchronization with the link partner. rx_serdes_clk

stat_lt_preset_from_rx

O This signal reflects the value of the preset control bit received in the control block from the link partner. rx_serdes_clk

stat_lt_initialize_from_rx

O This signal reflects the value of the initialize control bit received in the control block from the link partner. rx_serdes_clk
stat_lt_k_p1_from_rx0[1:0] O This 2-bit field indicates the update control bits for the k+1 coefficient, as received from the link partner in the control block. rx_serdes_clk
stat_lt_k0_from_rx0[1:0] O This 2-bit field indicates the update control bits for the k0 coefficient, as received from the link partner in the control block. rx_serdes_clk
stat_lt_k_m1_from_rx0[1:0] O This 2-bit field indicates the update control bits for the k-1 coefficient, as received from the link partner in the control block. rx_serdes_clk
stat_lt_stat_p1_from_rx0[1:0] O This 2-bit field indicates the update status bits for the k+1 coefficient, as received from the link partner in the status block. rx_serdes_clk
stat_lt_stat0_from_rx0[1:0] O This 2-bit field indicates the update status bits for the k0 coefficient, as received from the link partner in the status block. rx_serdes_clk
stat_lt_stat_m1_from_rx0[1:0] O This 2-bit field indicates the update status bits for the k-1 coefficient, as received from the link partner in the status block. rx_serdes_clk
ctl_lt_pseudo_seed0[10:0] I This 11-bit signal seeds the training pattern generator. tx_serdes_clk

ctl_lt_preset_to_tx

I This signal is used to set the value of the preset bit that is transmitted to the link partner in the control block of the training frame. tx_serdes_clk

ctl_lt_initialize_to_tx

I This signal is used to set the value of the initialize bit that is transmitted to the link partner in the control block of the training frame. tx_serdes_clk
ctl_lt_k_p1_to_tx0[1:0] I This 2-bit field is used to set the value of the k+1 coefficient update field that is transmitted to the link partner in the control block of the training frame. tx_serdes_clk
ctl_lt_k0_to_tx0[1:0] I This 2-bit field is used to set the value of the k0 coefficient update field that is transmitted to the link partner in the control block of the training frame. tx_serdes_clk
ctl_lt_k_m1_to_tx0[1:0] I This 2-bit field is used to set the value of the k-1 coefficient update field that is transmitted to the link partner in the control block of the training frame. tx_serdes_clk
ctl_lt_stat_p1_to_tx0[1:0] I This 2-bit field is used to set the value of the k+1 coefficient update status that is transmitted to the link partner in the status block of the training frame. tx_serdes_clk
ctl_lt_stat0_to_tx0[1:0] I This 2-bit field is used to set the value of the k0 coefficient update status that is transmitted to the link partner in the status block of the training frame. tx_serdes_clk
ctl_lt_stat_m1_to_tx0[1:0] I This 2-bit field is used to set the value of the k-1 coefficient update status that is transmitted to the link partner in the status block of the training frame. tx_serdes_clk
stat_lt_rx_sof[1-1:0] O This output is High for 1 RX SerDes clock cycle to indicate the start of the link training frame. rx_serdes_clk