This section contains information about upgrading from the legacy version of the Xilinx 10G EMAC IP to the new 1G/10G/25G Switching Ethernet Subsystem IP core.
The Xilinx 10G Ethernet MAC and the 1G/10G/25G Switching Ethernet Subsystem core are both designed to the specifications of the Ethernet IEEE 802.3 standard. There are significant differences in how some features are designed and/or handled. There are also differences in signal and parameter names and the corresponding AXI registers. Note that this section only outlines the features in the legacy 10G EMAC IP and compares them with the new 1G/10G/25G Switching Ethernet Subsystem IP core. For a list of new features or features exclusive to the new IP, refer to Product Specification.
The following features are different in the new1G/10G/25G Switching Ethernet Subsystem IP.
- Padding. The Pad field is not added by the 1G/10G/25G Switching Ethernet Subsystem IP. You must present a packet that meets the minimum
length to the IP core. When the IP core is configured to calculate and add the
FCS to the packet (
ctl_tx_fcs_ins_enable= 1), the minimum packet length is 60 bytes. If the FCS is calculated and added outside the IP core (
ctl_tx_fcs_ins_enable= 0), the minimum packet length is 64 bytes.
- IFG extension. The inter-frame gap (IFG/IPG) can be extended up to 12B using the parameter ctl_tx_ipg_value[2:0].
- Deficit Idle Count (DIC). The 10G/25G High Speed Ethernet IP has the DIC always enabled.
- Management Data Input/Output (MDIO) master. The 1G/10G/25G Switching Ethernet Subsystem IP does not provide an MDIO master. The contents of the appropriate MDIO registers are available in the status signals.
- Fault Handling The user logic must be designed differently for TX faults. Legacy 10G EMAC TX transmits RF or idles and drops packets by default if LF/RF is received. An option to disable fault transmission is provided. 1G/10G/25G Switching Ethernet Subsystem IP requires you to control if LF/RF are transmitted. You must provide the fault status signals as well.
- VLAN The new 1G/10G/25G Ethernet Subsystem IP provides no VLAN specific features. However you can set the ctl_rx_max_packet_len attribute appropriately to allow the standard VLAN frame (1522 B) and also design the user logic to handle any number of stacked VLAN tags.
- Enabling Link Training without Auto-negotiation On the legacy 10G IP, it appears that link training was always enabled (see below) whereas the 1G/10G/25G Switching Ethernet Subsystem IP performs link training after auto-negotiation and thus both features have to be enabled.
- Link Training Translation The legacy 10-BaseKR subsystem included logic that allowed it to be trained by a far-end device without user interaction. This feature is not available in the 1G/10G/25G Switching Ethernet Subsystem IP and the user logic must be designed to support this feature.
- Standalone MAC with 64-bit internal XGMII interface for connecting to XAUI/RXAUI The standalone MAC with the 64-bit internal XGMII interface is now available in 10G/25G High Speed Ethernet Subsystem v2.1 and later.
- External XGMII DDR interface to external PHY The external XGMII DDR interface to the external PHY option is now available as part of the 64-bit standalone MAC in 10G/25G High Speed Ethernet IP v2.1 and later.
- Pause Interface 1G/10G/25G Switching Ethernet Subsystem IP does not pause TX packet transmission when global pause frames are received this is left to user logic.
For more details, see 10G/25G High Speed Ethernet Subsystem Product Guide (PG210).