Normal Transmission - 2.7 English

1G/10G/25G Switching Ethernet Subsystem Product Guide (PG292)

Document ID
PG292
Release Date
2022-05-11
Version
2.7 English

The timings for a normal frame transfer are shown in the following figures for the 32-bit and 64-bit variants respectively. When the client wants to transmit a frame, it asserts the tx_axis_tvalid and places the data and control in tx_axis_tdata and tx_axis_tkeep in the same clock cycle. When this data is accepted by the core, indicated by tx_axis_tready being asserted, the client must provide the next cycle of data. If tx_axis_tready is not asserted by the core, the client must hold the current valid data value until it is. The end of packet is indicated to the core by tx_axis_tlast asserted for one cycle. The bits of tx_axis_tkeep are set appropriately to indicate the number of valid bytes in the final data transfer. tx_axis_tuser is also asserted to indicate a bad packet.

After tx_axis_tlast is deasserted, any data and control is deemed invalid until tx_axis_tvalid is next asserted.

Figure 1. Normal Frame Transfer - 32-bit
Figure 2. Normal Frame Transfer - 64-bit