Overview - 2.7 English

1G/10G/25G Switching Ethernet Subsystem Product Guide (PG292)

Document ID
PG292
Release Date
2022-05-11
Version
2.7 English

The following figure shows the instantiation of various modules and their hierarchy for a single core configuration of the ethernet_1_10_25g example design for a 32-bit MAC and PCS/PMA core when the GT (serial transceiver) is inside the IP core. (Serial Transceiver will always be a part of the example design for VersalĀ® ACAP).

Clocking helper blocks are used to generate the required clock frequency for the core.

Figure 1. 32-Bit MAC and PCS/PMA Single Core Example Design Hierarchy

The following figure shows the instantiation of various modules and their hierarchy for a single core configuration of the ethernet_1_10_25g_0 example design for a 64-bit MAC and PCS/PMA core configuration.

Figure 2. 64-Bit MAC and PCS/PMA Single Core Example Design Hierarchy

The following figure shows the instantiation of various modules when their hierarchy for a single core configuration of ethernet_1_10_25g_0 example design for a 32-bit PCS/PMA core.

Figure 3. 32-Bit PCS Only Single Core Example Design Hierarchy

The following user interfaces are available for different configurations.

  • MAC/PCS configuration:
    • AXI4-Stream for datapath interface
    • AXI4-Lite for control and statistics interface
  • PCS configuration:
    • XGMII interface
    • GMII interface
    • AXI4-Lite for control and statistics interface

The ethernet_1_10_25g_0 module is used to generate the data packets for sanity testing. The packet generation and checking is controlled by a FSM module.

The optional modules are described as follows:

TX / RX pipeline register
The TX pipeline register double synchronizes the data from the core to the GT with respect to the tx_clk. The RX pipeline register double synchronizes the data from the GT to the core with respect to the rx_serdes_clk.
Note: If you select Auto-Negotiation in the Vivado IDE, the operation is only performed with the 10G data rate. After the Auto-Negotiation is complete, the core is switched to mission mode. For parallel detection, the core is switched to 1G data rate.

The following figure shows the instantiation of various modules and their hierarchy for multiple core configuration of the ethernet_1_10_25g_0 example design for a 32-bit PCS/PMA core.

Figure 4. 32-Bit MAC and PCS/PMA Multiple Cores Example Design Hierarchy

The following figure shows the instantiation of various modules and their hierarchy for the multiple core configuration of the ethernet_1_10_25g_0 example design for a 64-bit MAC and PCS/PMA core.

Figure 5. 64-Bit MAC and PCS/PMA Multiple Core Example Design Hierarchy

The following figure shows the instantiation of various modules and their hierarchy for the multiple core configuration of the ethernet_1_10_25g_0 example design for a 32-bit PCS/PMA core.

Figure 6. 32-Bit PCS/PMA Only Multiple Core Example Design Hierarchy