Pause Interface - 2.7 English

1G/10G/25G Switching Ethernet Subsystem Product Guide (PG292)

Document ID
PG292
Release Date
2022-05-11
Version
2.7 English

The following tables show the Pause interface I/O ports.

Table 1. Pause Interface - Control Ports
Name I/O Description Clock Domain
ctl_rx_pause_enable[8:0] I RX pause enable signal. This input is used to enable the processing of the pause quanta for the corresponding priority. Note that this signal only affects the RX user interface, not the pause processing logic. rx_clk_out
ctl_tx_pause_enable[8:0] I TX pause enable signal. This input is used to enable the processing of the pause quanta for the corresponding priority. This signal gates transmission of pause packets. tx_clk_out
Table 2. Pause Interface - RX Path
Name I/O Description Clock Domain
ctl_rx_enable_gcp I A value of 1 enables global control packet processing. rx_clk_out
ctl_rx_check_mcast_gcp I A value of 1 enables global control multicast destination address processing. rx_clk_out
ctl_rx_check_ucast_gcp I A value of 1 enables global control unicast destination address processing. rx_clk_out
ctl_rx_pause_da_ucast[47:0] I Unicast destination address for pause processing. rx_clk_out
ctl_rx_check_sa_gcp I A value of 1 enables global control source address processing. rx_clk_out
ctl_rx_pause_sa[47:0] I Source address for pause processing. rx_clk_out
ctl_rx_check_etype_gcp I A value of 1 enables global control ethertype processing. rx_clk_out
ctl_rx_check_opcode_gcp I A value of 1 enables global control opcode processing. rx_clk_out
ctl_rx_opcode_min_gcp[15:0] I Minimum global control opcode value. rx_clk_out
ctl_rx_opcode_max_gcp[15:0] I Maximum global control opcode value. rx_clk_out
ctl_rx_etype_gcp[15:0] I Ethertype field for global control processing. rx_clk_out
ctl_rx_enable_pcp I A value of 1 enables priority control packet processing. rx_clk_out
ctl_rx_check_mcast_pcp I A value of 1 enables priority control multicast destination address processing. rx_clk_out
ctl_rx_check_ucast_pcp I A value of 1 enables priority control unicast destination address processing. rx_clk_out
ctl_rx_pause_da_mcast[47:0] I Multicast destination address for pause processing. rx_clk_out
ctl_rx_check_sa_pcp I A value of 1 enables priority control source address processing. rx_clk_out
ctl_rx_check_etype_pcp I A value of 1 enables priority control ethertype processing. rx_clk_out
ctl_rx_etype_pcp[15:0] I Ethertype field for priority control processing. rx_clk_out
ctl_rx_check_opcode_pcp I A value of 1 enables priority control opcode processing. rx_clk_out
ctl_rx_opcode_min_pcp[15:0] I Minimum priority control opcode value. rx_clk_out
ctl_rx_opcode_max_pcp[15:0] I Maximum priority control opcode value. rx_clk_out
ctl_rx_enable_gpp I A value of 1 enables global pause packet processing. rx_clk_out
ctl_rx_check_mcast_gpp I A value of 1 enables global pause multicast destination address processing. rx_clk_out
ctl_rx_check_ucast_gpp I A value of 1 enables global pause unicast destination address processing. rx_clk_out
ctl_rx_check_sa_gpp I A value of 1 enables global pause source address processing. rx_clk_out
ctl_rx_check_etype_gpp I A value of 1 enables global pause ethertype processing. rx_clk_out
ctl_rx_etype_gpp[15:0] I Ethertype field for global pause processing. rx_clk_out
ctl_rx_check_opcode_gpp I A value of 1 enables global pause opcode processing. rx_clk_out
ctl_rx_opcode_gpp[15:0] I Global pause opcode value. rx_clk_out
ctl_rx_enable_ppp I A value of 1 enables priority pause packet processing. rx_clk_out
ctl_rx_check_mcast_ppp I A value of 1 enables priority pause multicast destination address processing. rx_clk_out
ctl_rx_check_ucast_ppp I A value of 1 enables priority pause unicast destination address processing. rx_clk_out
ctl_rx_check_sa_ppp I A value of 1 enables priority pause source address processing. rx_clk_out
ctl_rx_check_etype_ppp I A value of 1 enables priority pause ethertype processing. rx_clk_out
ctl_rx_etype_ppp[15:0] I Ethertype field for priority pause processing. rx_clk_out
ctl_rx_check_opcode_ppp I A value of 1 enables priority pause opcode processing. rx_clk_out
ctl_rx_opcode_ppp[15:0] I Priority pause opcode value. rx_clk_out
stat_rx_pause_req[8:0] O Pause request signal. When the RX receives a valid pause frame, it sets the corresponding bit of this bus to a 1 and keep it at 1 until the pause packet has been processed. rx_clk_out
ctl_rx_pause_ack[8:0] I Pause acknowledge signal. This bus is used to acknowledge the receipt of the pause frame from the user logic. rx_clk_out
ctl_rx_check_ack I Wait for acknowledge. If this input is set to 1, the core uses the ctl_rx_pause_ack[8:0] bus for pause processing. If this input is set to 0, ctl_rx_pause_ack[8:0] is not used. rx_clk_out
ctl_rx_forward_control I A value of 1 indicates that the core forwards control packets. A value of 0 causes core to drop control packets. rx_clk_out
stat_rx_pause_valid[8:0] O Indicates that a pause packet was received and the associated quanta on the stat_rx_pause_quanta[8:0][15:0] bus is valid and must be used for pause processing. If an 802.3x MAC Pause packet is received, bit[8] is set to 1. rx_clk_out
stat_rx_pause_quanta[8:0][15:0] O These nine buses indicate the quanta received for each of the eight priorities in priority based pause operation and global pause operation. If an 802.3x MAC Pause packet is received, the quanta is placed in value [8]. rx_clk_out
Table 3. Pause Interface – TX Path
Name I/O Description Clock Domain
ctl_tx_pause_req[8:0] I If a bit of this bus is set to 1, the core transmits a pause packet using the associated quanta value on the ctl_tx_pause_quanta[8:0][15:0] bus. If bit[8] is set to 1, a global pause packet is transmitted. All other bits cause a priority pause packet to be transmitted. tx_clk_out
ctl_tx_pause_quanta[8:0][15:0] I These nine buses indicate the quanta to be transmitted for each of the eight priorities in priority based pause operation and the global pause operation. The value for ctl_tx_pause_quanta[8] is used for global pause operation. All other values are used for priority pause operation. tx_clk_out
ctl_tx_pause_refresh_timer [8:0][15:0] I These nine buses set the retransmission time of pause packets for each of the eight priorities in priority based pause operation and the global pause operation. The value for ctl_tx_pause_refresh_timer[8] is used for global pause operation. All other values are used for priority pause operation. tx_clk_out
ctl_tx_da_gpp[47:0] I Destination address for transmitting global pause packets. tx_clk_out
ctl_tx_sa_gpp[47:0] I Source address for transmitting global pause packets. tx_clk_out
ctl_tx_ethertype_gpp[15:0] I Ethertype for transmitting global pause packets. tx_clk_out
ctl_tx_opcode_gpp[15:0] I Opcode for transmitting global pause packets. tx_clk_out
ctl_tx_da_ppp[47:0] I Destination address for transmitting priority pause packets. tx_clk_out
ctl_tx_sa_ppp[47:0] I Source address for transmitting priority pause packets. tx_clk_out
ctl_tx_ethertype_ppp[15:0] I Ethertype for transmitting priority pause packets. tx_clk_out
ctl_tx_opcode_ppp[15:0] I Opcode for transmitting priority pause packets. tx_clk_out
ctl_tx_resend_pause I Retransmit pending pause packets. When this input is sampled as 1, all pending pause packets are retransmitted as soon as possible (that is, after the current packet in flight is completed) and the retransmit counters are reset. This input should be pulsed to 1 for one cycle at a time. tx_clk_out
stat_tx_pause_valid[8:0] O If a bit of this bus is set to 1, the core has transmitted a pause packet. If bit[8] is set to 1, a global pause packet is transmitted. All other bits cause a priority pause packet to be transmitted. tx_clk_out