Port Descriptions - 2.7 English

1G/10G/25G Switching Ethernet Subsystem Product Guide (PG292)

Document ID
PG292
Release Date
2022-05-11
Version
2.7 English
Table 1. RS-FEC Port List and Descriptions
Port Direction Description Clock Domain
RS-FEC Control Signals
ctl_rsfec_ieee_error_indication_mode Input

The setting on this bit takes effect after rx_resetn has been asserted Low (~rx_serdes_reset). New value is sampled on first cycle on reset.

  • 1: Core conforms to the IEEE RS-FEC specification.
  • 0: If ctl_rx_rsfec_enable_correction and ctl_rx_rsfec_enable_indication are set to zero, the RS decoder is bypassed.
rx_serdes_clk
ctl_rsfec_consortium_25g Input Switches between IEEE Clause 108 and 25G Ethernet Consortium mode.

The setting on this bit takes effect after rx_resetn has been asserted Low (~rx_serdes_reset). New value is sampled on first cycle on reset.

  • 1 = 25G Consortium specification mode.
  • 0 = IEEE 802.3by mode.

Note that some variants of the 1/10/25G Subsystem can have individual RX and TX consortium signals.

rx_serdes_clk
ctl_rsfec_enable Input

The setting on this bit takes effect after rx_resetn has been asserted Low (~rx_serdes_reset). New value is sampled on first cycle on reset.

Enable RS-FEC function. Note that some variants of the 1/10/25G Subsystem can have individual RX and TX enable signals.

rx_serdes_clk
ctl_rx_rsfec_enable_correction Input

The setting on this bit takes effect after rx_resetn has been asserted Low (~rx_serdes_reset). New value is sampled on first cycle on reset.

Equivalent to MDIO register 1.200.0

  • 0: Decoder performs error detection without error correction (see IEEE 802.3802.3by section 91.5.3.3).
  • 1: the decoder also performs error correction.
rx_serdes_clk
ctl_rx_rsfec_enable_indication Input

The setting on this bit takes effect after rx_resetn has been asserted Low (~rx_serdes_reset). New value sampled on first cycle on reset.

Equivalent to MDIO register 1.200.1

  • 0: Bypass the error indication function (see IEEE Std 802.3by section 91.5.3.3).
  • 1: Decoder indicates errors to the PCS sublayer.
rx_serdes_clk
ctl_rx_vl_length_minus1[15:0] Input Normally set to 20,479 (4FFF hex). The normal value is equivalent to (16,383 x 5 -4) = 81,916.  
ctl_rx_vl_marker_id0[63:0] Input Equivalent to the RX PCS lane 0 alignment marker defined in IEEE 802.3 Clause 82 for 40 G Ethernet.  
ctl_rx_vl_marker_id1[63:0] Input Equivalent to the PCS lane 1 alignment marker.  
ctl_rx_vl_marker_id2[63:0] Input Equivalent to the PCS lane 2 alignment marker.  
ctl_rx_vl_marker_id3[63:0] Input Equivalent to the PCS lane 3 alignment marker.  
ctl_tx_vl_length_minus1[15:0] Input Normally set to 20479 (decimal). The normal value is equivalent to (16,383 x 5 -4) = 81,916.  
ctl_tx_vl_marker_id0[63:0] Input Equivalent to the TX PCS lane 0 alignment marker defined in IEEE 802.3 Clause 82 for 40 G Ethernet.  
ctl_tx_vl_marker_id1[63:0] Input Equivalent to the PCS lane 1 alignment marker.  
ctl_tx_vl_marker_id2[63:0] Input Equivalent to the PCS lane 2 alignment marker.  
ctl_tx_vl_marker_id3[63:0] Input Equivalent to the PCS lane 3 alignment marker  
RS-FEC Status Signals
stat_rx_rsfec_corrected_cw_inc Output Increment for corrected errors. rx_serdes_clk
stat_rx_rsfec_uncorrected_cw_inc Output Increment for uncorrected errors. rx_serdes_clk
stat_rx_rsfec_err_count_inc[2:0] Output Increment for detected errors. rx_serdes_clk
stat_rx_rsfec_hi_ser Output Set to one if the number of RS-FEC symbol errors in a window of 8192 codewords exceeds the threshold K = 417 and is set to zero otherwise. rx_serdes_clk
stat_rx_rsfec_lane_alignment_status Output A value of 1 indicates that the RX RS-FEC block has achieved alignment on the data from the transceiver. rx_serdes_clk
stat_tx_rsfec_lane_alignment_status Output A value of 1 indicates that the TX RS-FEC block has achieved alignment on the incoming PCS data. rx_serdes_clk