Register Descriptions - 2.7 English

1G/10G/25G Switching Ethernet Subsystem Product Guide (PG292)

Document ID
PG292
Release Date
2022-05-11
Version
2.7 English

This section contains descriptions of the configuration registers. In the cases where the features described in the bit fields are not present in the IP core, the bit field reverts to RESERVED. The following descriptions cover only the registers that have been modified with respect to default operation of the respective IPs in applicable mode. For further information on register interface definitions (not defined in this guide), see 10G/25G High Speed Ethernet Subsystem Product Guide (PG210) or 1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047).