Revision History - 2.7 English

1G/10G/25G Switching Ethernet Subsystem Product Guide (PG292)

Document ID
PG292
Release Date
2022-05-11
Version
2.7 English

The following table shows the revision history for this document.

Section Revision Summary
05/11/2022 Version 2.7
General updates Added support for Auto-negotiation and link Training for MAC+PCS/PMA 64-bit for 1G/10G rate for GTH Transceiver.
IP Facts Corrected link.
10/27/2021 Version 2.7
Simulation Speed Up Updated for supported simulators.
08/11/2021 Version 2.7
IP Facts Corrected link.
Performance and Resource Utilization Corrected link.
08/06/2021 Version 2.7
General updates
  • Added GTH support for the 64-bit variant.
  • Added 1G/10G switching support for the 64-bit variant.
02/05/2021 Version 2.6
General updates
  • Added support for Versal ACAP.
  • Added support for RSFEC(Clause 108) for MAC+PCS/PMA 64-bit.
  • Added Preemption support for MAC+PCS/PMA 64-bit for non-Versal device.
Register Space Added new registers.
Register Descriptions
  • Added GIG_EHERNET_PCS_PMA_CONFIGURATION_VECTOR:0x1000.
  • Added GIG_ETHERNET_PCS_PMA_STATUS_VECTOR:0x1004.
LogiCORE Example Design Clocking and Resets Updated figures.
802.1cm Preemption Feature Added.
Port Descriptions Updated.
Customizing and Generating the Subsystem Updated figures.
06/03/2020 Version 2.5
STAT_RX_STATUS_REG1: 0404 Updated bit 0 Type.
LogiCORE Example Design Clocking and Resets Reset signal name updated in figures.
Board Testing Steps for Auto-Negotiation and Link Training Using AXI4-Lite Interface Clarified text.
Customizing and Generating the Subsystem Screenshots updated.

Debugging Auto-Negotiation and Link Training

New debugging topics added.
10/30/2019 Version 2.4
Link Training Added the board testing steps of Ethernet Subsystem core for Auto Negotiation and Link Training with AXI4-Lite Interface.
Configuration Tab Updated the Notes section with STATISTICS_COUNTERS_SIZE parameter details.
MAC Options Tab Updated to include the Include System Timer Syncers options.
Debugging

Added a new section Migrating from the Legacy XGEMAC.

05/22/2019 Version 2.3
Auto-Negotiation (Clause 37) Added Auto-Negotiation Clause 37 information.
Miscellaneous Status/Control Signals Added signal_detect port.
Configuration Tab Updated configuration options table with Statistics Resource Type, Include Statistics Counters, and updated Auto-Negotiation options (Clause 73 and Clause 37).
12/05/2018 Version 2.2
XGMII Interfaces Added timing diagrams and descriptions.
Using the Client-Side GMII Interface Added timing diagrams and descriptions.
Link Training Ports Added Link Training Ports table.
IEEE 802.3 Clause 74 FEC Interface

Added IEEE 802.3 Clause 74 FEC Interface Control/Status/Statistics Signals table.

Pause Interface Added Pause Interface I/O ports.

Auto-Negotiation and Link Training Clocking

Added Auto-Negotiation Clocking Architecture figure.
Pause Processing Added Pause Processing section.
Link Training Added Link Training section.
Configuration Register Map 1G/10G/25G Ethernet Subsystem Added items to Configuration Register Map.
Status Register Map for 1G/10G/25G Ethernet Subsystem Added items to Status Register Map.
Statistics Counters Added items to Statistics Counters.
Configuration Tab Added further PCS/PMA options.
MAC Options Tab Added Flow Control section.
Include GT Subcore in Example Design Ports New table for ports available when the Include GT subcore in Example Design option is selected.
TX Pause Interface Control/Status/Statistics Signals

RX Pause Interface Control/Status/Statistics Signals

Clause 74 FEC Interface Control/Status/Statistics Signals

New tables for TX Pause Interface Control/Status/Statistics Signals, RX Pause Interface Control/Status/Statistics Signals, and Clause 74 FEC Interface Control/Status/Statistics Signals in the Core XCI Top Level Port List.
06/06/2018 Version 2.1
General updates

Auto-Negotiation (Clause 37) and Auto-Negotiation Ports

Auto-Negotiation and Link Training Clocking

AN Interface Control/Status/Statistics Signals

  • Updated the Example Design Clocking and Reset diagrams.
  • Added Optional Clause 73 Auto-Negotiation with Parallel Detection support.
  • Added the clocking architecture for the Auto-Negotiation function.
  • Added AN Interface Control / Status / Statistics Signals table.
04/04/2018 Version 2.0
General updates Initial release.
12/20/2017 Version 1.0
General updates Xilinx Confidential. Initial release under NDA only.