This document details the features of the 1G/10G/25G Ethernet Subsystem dynamically switching PCS/PMA and MAC core. The 10G/25G Ethernet Subsystem is defined by the 25G Ethernet Consortium. 10G PCS functionality is defined by IEEE Standard 802.3, 2015, Clause 49, Physical Coding Sublayer (PCS) for 64B/66B, type 10GBASE-R. 1G PCS functionality is defined in Clause 36. For 25G operation, clock frequencies are increased to provide a serial interface operating at 25.78125 Gbps to leverage the latest high-speed serial transceivers. The low latency design is optimized for AMD UltraScale+™ architecture devices.