TX Pause Generation - 2.7 English

1G/10G/25G Switching Ethernet Subsystem Product Guide (PG292)

Document ID
PG292
Release Date
2022-05-11
Version
2.7 English

You can request a pause packet to be transmitted using the ctl_tx_pause_req[8:0] and ctl_tx_pause_enable[8:0] input buses. Bit [8] corresponds to global pause packets and bits [7:0] correspond to priority pause packets.

Each bit of this bus must be held at a steady state for a minimum of 16 cycles before the next transition.

CAUTION:
Requesting both global and priority pause packets at the same time results in unpredictable behavior and must be avoided.

The contents of the pause packet are determined using the following input pins.

Global pause packets:

ctl_tx_da_gpp[47:0] 
ctl_tx_sa_gpp[47:0]
ctl_tx_ethertype_gpp[15:0]
ctl_tx_opcode_gpp[15:0]
ctl_tx_pause_quanta8[15:0]

Priority pause packets:

ctl_tx_da_ppp[47:0] 
ctl_tx_sa_ppp[47:0] 
ctl_tx_ethertype_ppp[15:0] 
ctl_tx_opcode_ppp[15:0] 
ctl_tx_pause_quanta0[15:0] 
ctl_tx_pause_quanta1[15:0] 
ctl_tx_pause_quanta2[15:0] 
ctl_tx_pause_quanta3[15:0] 
ctl_tx_pause_quanta4[15:0] 
ctl_tx_pause_quanta5[15:0] 
ctl_tx_pause_quanta6[15:0] 
ctl_tx_pause_quanta7[15:0]

The 1G/10G/25G Ethernet Subsystem automatically calculates and adds the FCS to the packet. For priority pause packets the 1G/10G/25G Ethernet Subsystem also automatically generates the enable vector based on the priorities that are requested.

To request a pause packet, you must set the corresponding bit of the ctl_tx_pause_req[8:0] and ctl_tx_pause_enable[8:0] bus to 1 and keep it at 1 for the duration of the pause request (that is, if these inputs are set to 0, all pending pause packets are canceled). Pause is canceled by sending out an additional pause packet with the corresponding pause quanta set to 0. The 1G/10G/25G Ethernet Subsystem transmits the pause packet immediately after the current packet in flight is completed.

Important: Each bit of this bus must be held at a steady state for a minimum of 16 cycles before the next transition.

To retransmit pause packets, the 1G/10G/25G Ethernet Subsystem maintains a total of nine independent timers; one for each priority and one for global pause. These timers are loaded with the value of the corresponding input buses. After a pause packet is transmitted the corresponding timer is loaded with the corresponding value of the ctl_tx_pause_refresh_timer[8:0] input bus. When a timer times out, another packet for that priority (or global) is transmitted as soon as the current packet in flight is completed. Additionally, you can manually force the timers to 0, and therefore force a retransmission, by setting the ctl_tx_resend_pause input to 1 for one clock cycle.

To reduce the number of pause packets for priority mode operation, a timer is considered timed out if any of the other timers time out. Additionally, while waiting for the current packet in flight to be completed, any new timer that times out or any new requests are merged into a single pause frame. For example, if two timers are counting down, and you send a request for a third priority, the two timers are forced to be timed out and a pause packet for all three priorities is sent as soon as the current in-flight packet (if any) is transmitted. Similarly, if one of the two timers times out without an additional request, both timers are forced to be timed out and a pause packet for both priorities is sent as soon as the current in-flight packet (if any) is transmitted.

You can stop pause packet generation by setting the appropriate bits of ctl_tx_pause_req[8:0] or ctl_tx_pause_enable[8:0] to 0.