Transceiver Interface - 2.7 English

1G/10G/25G Switching Ethernet Subsystem Product Guide (PG292)

Document ID
PG292
Release Date
2022-05-11
Version
2.7 English

The following table shows the transceiver I/O ports for the 1G/10G/25G Ethernet Subsystem. See Clocking for details on each clock domain.

Table 1. Transceiver I/O
Name I/O Description Clock Domain
gt_tx_reset I Reset for the gigabit transceiver (GT) TX. Async
gt_rx_reset I GT RX reset. Async
ctl_gt_reset_all I Active-High asynchronous reset for the transceiver startup Finite State Machine (FSM). Note that this signal also initiates the reset sequence for the entire 1G/10G/25G Ethernet Subsystem. Async
refclk_n0 I Differential reference clock input for the SerDes, negative phase. See Clocking.
refclk_p0 I Differential reference clock input for the SerDes, positive phase. See Clocking.
rx_serdes_data_n0 I Serial data from the line; negative phase of the differential signal See Clocking.
rx_serdes_data_p0 I Serial data from the line; positive phase of the differential signal See Clocking.
tx_serdes_data_n0 O Serial data to the line; negative phase of the differential signal. See Clocking.
tx_serdes_data_p0 O Serial data to the line; positive phase of the differential signal. See Clocking.
tx_serdes_clk O When present, same as tx_clk_out. See Clocking.