Transmit - 2.7 English

1G/10G/25G Switching Ethernet Subsystem Product Guide (PG292)

Document ID
PG292
Release Date
2022-05-11
Version
2.7 English

The Link Training transmit block constructs a 4,384-bit frame which contains a frame delimiter, control channel, and link training sequence. It is formatted as shown in the following figure.

Figure 1. Link Training Frame Structure

Xilinx recommends that the control channel bits not be changed by the Link Training algorithm while the transmit state machine is in the process of transmitting them, or they can be received incorrectly, possibly resulting in a DME error. This time begins when tx_SOF is asserted and ends at least 288 bit times later, or approximately 30 ns.

Although the coefficient and status contain 128 bit times at the line rate, the actual signaling rate for these two fields is reduced by a factor of eight. Therefore the DME clock rate is one quarter of the line rate.