The core has two AXI4-Stream Interfaces, for express (tx_axis_e_*) and preempt traffic (tx_axis_p_*), when the core is generated with the optional TSN feature. For details, refer to AXI4-Stream Interface.
Note: The same descriptions and rules apply to
these signals as the ones in AXI4-Stream Interface.
There is an option to insert a FIFO on the preempt interface during core generation. When this FIFO is inserted, the ingress frame will be buffered and only when the complete error-free frames are available in this FIFO will it be made available on the AXI4-Stream interface.