XGMII Interfaces - 2.7 English

1G/10G/25G Switching Ethernet Subsystem Product Guide (PG292)

Document ID
PG292
Release Date
2022-05-11
Version
2.7 English

Internal 32-bit SDR Client-Side Interface

The mapping of lanes to data bits is shown in the following table. The lane number is also the index of the control bit for that particular lane; for example, tx_mii_c[2] and tx_mii_d[23:16] are the control and data bits respectively for lane 2.

Table 1. Lanes for Internal 32-bit Client-Side Interface
Lane tx_mii_d, rx_mii_d Bits
0 7:0
1 15:8
2 23:16
3 31:24

Definitions of Control Characters

Reference is regularly made to certain XGMII control characters signifying Start, Terminate, Error, and others. These control characters all have in common that the control line for that lane is 1 for the character and a certain data byte value. The relevant characters are defined in the IEEE Std. 802.3 and are reproduced in the following table for reference.

Table 2. Partial List of XGMII Characters
Data (Hex) Control Name, Abbreviation
00 to FF 0 Data (D)
07 1 Idle (I)
FB 1 Start (S)
FD 1 Terminate (T)
FE 1 Error (E)