An AUX write transaction is initiated by setting up the AUX_ADDRESS, and
writing the data to the AUX_WRITE_FIFO followed by a write to the AUX_COMMAND register with
the code 0x08. Writing the command register begins the AUX channel
transaction. The host should wait until either a reply received event or reply timeout event
is detected. These events are detected by reading INTERRUPT_STATUS registers (either in ISR or
polling mode).
When the reply is detected, the host should read the AUX_REPLY_CODE register
and look for the code 0x00 indicating that the AUX channel has successfully
acknowledged the transaction.
The following figure shows the flow of an AUX write transaction.
Figure 1. AUX Write Transaction
