The subsystem uses the Xilinx® AXI Smartconnect IP core, as a smartconnect which contains an AXI4-Lite interface. For more details on the AXI Smartconnect functionality, see the SmartConnect LogiCORE IP Product Guide (PG247). The following figure shows the AXI slave structure within the DisplayPort 1.4 TX Subsystem.
Figure 1. AXI4-Lite Interconnect within DisplayPort 1.4 TX Subsystem
- The Video Timing Controller IP core is present only when subsystem is generated in AXI4-Stream interface mode.
- For MST with N streams, there are N Video Timing Controller IP cores. See Address Map Example.