This section describes the link clock (
tx_lnk_clk) and the video clock (
tx_vid_clk_stream1). The AXI4-Stream to Video
Bridge can handle asynchronous clocking. The value is based on the Consumer Electronics
Association (CEA)/VESA Display Monitor Timing (DMT) standard for given video resolutions.
tx_lnk_clk is a link
clock input to the DisplayPort 1.4 TX Subsystem generated by the Video PHY
(GT). The frequency of
<line_rate>/20 MHz for 16-bit interface.
hdcp_ext_clk input can
be driven from external MMCM or BUFGCDIV where it has a frequency requirement of
In both, native and AXI4-stream modes TX video clock value is based on the Consumer Electronics Association (CEA)/VESA Display Monitor Timing (DMT) standard for given video resolutions.
The core uses six clock domains:
txoutclkfrom the Video PHY is connected to the TX subsystem link clock. Most of the core operates in the link clock domain. This domain is based on the
lnk_clk_p/nreference clock for the transceivers. The link rate switching is handled by a DRP state machine in the core PHY later. When the lanes are running at 2.7 Gb/s,
lnk_clkoperates at 135 MHz. When the lanes are running at 1.62 Gb/s,
lnk_clkoperates at 81 MHz. When the lanes are running at 5.4 Gb/s,
lnk_clkoperates at 270 MHz. When the lanes are running at 8.1 Gb/s,
lnk_clkoperates at 405 MHz.Note:
link_rate/20, when the GT data width is 16-bit.
- This is the primary user interface clock. It is based on the
DisplayPort Standard, the video clock can be derived from the link clock using
nvid. In addition,
vid_clkshould be at least [(Vtotal x Htotal x frames per second)/pixels per clock]. For YCbCr420 colorimetry, the
vid_clkfrequency will be half of the actual
- This is the processor domain. It has been tested to run as fast as 135
MHz. The AUX clock domain is derived from this domain, but requires no additional
s_axi_aclkclock is connected to a free-running clock input.
gtwiz_reset_clk_freerun_inis required by the reset controller helper block to reset the transceiver primitives. A new GUI parameter is added for AXI_Frequency, when the DisplayPort IP is targeted to UltraScale FPGA.
- This is the audio interface clock. The frequency will be equal to 512 × audio sample rate.
- This clock is used by the source audio streaming interface. This clock should be = 512 × audio sample rate.
- This clock is used by the sink audio streaming interface. This clock should be = 512 × audio sample rate.
For more information on clocking, see the Video PHY Controller LogiCORE IP Product Guide (PG230).