Main Stream Attributes - 3.1 English

DisplayPort 1.4 TX Subsystem Product Guide

Document ID
PG299
Release Date
2022-10-19
Version
3.1 English

For more details on the DisplayPort Standard, see the VESA DisplayPort Standard v1.4.

Table 1. Main Stream Attributes
Offset Access Type Description
0x180 R/W MAIN_STREAM_HTOTAL. Specifies the total number of clocks in the horizontal framing period for the main stream video signal.

[15:0] - Horizontal line length total in clocks.

0x184 R/W MAIN_STREAM_VTOTAL. Provides the total number of lines in the main stream video frame.

[15:0] - Total number of lines per video frame.

0x188 R/W

MAIN_STREAM_POLARITY. Provides the polarity values for the video sync signals. Polarity information is packed and sent in the MSA packet. See the Main Stream Attribute Data Transport section of the VESA DisplayPort Standard (VESA website).

0 = Active-High

1 = Active-Low

[1] - VSYNC_POLARITY: Polarity of the vertical sync pulse.

[0] - HSYNC_POLARITY: Polarity of the horizontal sync pulse.

0x18C R/W MAIN_STREAM_HSWIDTH. Sets the width of the horizontal sync pulse.

[14:0] - Horizontal sync width in clock cycles.

0x190 R/W MAIN_STREAM_VSWIDTH. Sets the width of the vertical sync pulse.

[14:0] - Width of the vertical sync in lines.

0x194 R/W MAIN_STREAM_HRES. Horizontal resolution of the main stream video source.

[15:0] - Number of active pixels per line of the main stream video.

0x198 R/W MAIN_STREAM_VRES. Vertical resolution of the main stream video source.

[15:0] - Number of active lines of video in the main stream video source.

0x19C R/W MAIN_STREAM_HSTART. Number of clocks between the leading edge of the horizontal sync and the start of active data.

[15:0] - Horizontal start clock count.

0x1A0 R/W MAIN_STREAM_VSTART. Number of lines between the leading edge of the vertical sync and the first line of active data.

[15:0] - Vertical start line count.

0x1A4 R/W

MAIN_STREAM_MISC0. Miscellaneous stream attributes.

[7:0] - Implements the attribute information contained in the DisplayPort MISC0 register described in section 2.2.4 of the standard.

[12] - 0: Default Behavior. 1: Enables mode to sync Ext packet transmission with Vsync event.

[11] - Maud control (Advanced Users)

[10] - Audio Only Mode. When enabled, controller inserts information/timestamp packets every 512 BS symbols. By default the value is 0.

[9] - Sync/Async Mode for Audio

[8] - Override Audio Clocking Mode

[7:5] - Bit depth per color/component

[4] - YCbCr Colorimetry

[3] - Dynamic Range

[2:1] - Component Format

[0] - Synchronous Clock

0x1A8 R/W

MAIN_STREAM_MISC1. Miscellaneous stream attributes.

[7:0] - Implements the attribute information contained in the DisplayPort MISC1 register described in section 2.2.4 of the standard.

[5:3] - Reserved

[2:1] - Stereo video attribute

[0] - Interlaced vertical total even

0x1AC R/W M-VID . If synchronous clocking mode is used, this register must be written with the M value as described previously of the standard. When in asynchronous clocking mode, the M value for the video stream is automatically computed by the source core and written to the main stream. These values are not written into the M-VID register for readback.

[23:0] - Unsigned M value.

0x1B0 R/W TRANSFER_UNIT_SIZE. Sets the size of a transfer unit in the framing logic On reset, transfer size is set to 64. This register must be written as described in section 2.2.1.4.1 of the standard.

[6:0] - This number should be 32 or 64 and is set to a fixed value that depends on the inbound video mode. Note that bit 0 cannot be written (the transfer unit size is always even).

0x1B4 R/W N-VID . If synchronous clocking mode is used, this register must be written with the N value as described in section 2.2.3 of the standard. When in asynchronous clocking mode, the M value for the video stream is automatically computed by the source core and written to the main stream. These values are not written into the N-VID register for readback.

[23:0] - Unsigned N value.

0x1B8 R/W

USER_PIXEL_WIDTH. Selects the width of the user data input port. Use quad pixel mode in MST . In SST, the user pixel width should always be equal to the active lane count generated in hardware.

[2:0]:
  • 1 - Single pixel wide interface
  • 2 - Dual pixel wide interface. Valid for designs with 2 or 4 lanes.
  • 4 - Quad pixel wide interface Valid for designs with 4 lanes only.
0x1BC R/W USER_DATA_COUNT_PER_LANE. This register is used to translate the number of pixels per line to the native internal 16-bit datapath.

If (HRES × bits per pixel) is divisible by 16, then word_per_line = ((HRES × bits per pixel)/16)

Else

word_per_line = (INT((HRES × bits per pixel)/16)) + 1

For single-lane design:

Set USER_DATA_COUNT_PER_LANE = words_per_line - 1

For 2-lane design:

If words_per_line is divisible by 2, then set USER_DATA_COUNT_PER_LANE = words_per_line - 2

Else

Set USER_DATA_COUNT_PER_LANE = words_per_line + MOD(words_per_line,2) - 2

For 4-lane design:

If words_per_line is divisible by 4, then set USER_DATA_COUNT_PER_LANE = words_per_line - 4

Else

Set USER_DATA_COUNT_PER_LANE = words_per_line + MOD(words_per_line,4) - 4

Note: When MST mode is selected, irrespective of the user selected value of "number of lanes", "USER_DATA_COUNT_PER_LANE" should always be calculated, considering number of lanes as 4. This is because, DP core always works in 4 lane mode in MST.
0x1C0 R/W MAIN_STREAM_INTERLACED. Informs the DisplayPort transmitter main link that the source video is interlaced. By setting this bit to a 1, the core sets the appropriate fields in the VBID value and Main Stream Attributes. This bit must be set to a 1 for the proper transmission of interlaced sources.

[0] - Set to a 1 when transmitting interlaced images.

0x1C4 R/W MIN_BYTES_PER_TU. Programs source to use MIN number of bytes per transfer unit. The calculation should be done based on the DisplayPort Standard.

[6:0] - Set the value to INT((VIDEO_BW/LINK_BW)*TRANSFER_UNIT_SIZE)

0x1C8 R/W FRAC_BYTES_PER_TU. Calculating MIN bytes per TU is often not a whole number. This register is used to hold the fractional component.

[9:0] - The fraction part of ((VIDEO_BW/LINK_BW) × TRANSFER_UNIT_SIZE) scaled by 1024 is programmed in this register.

0x1CC R/W INIT_WAIT. This register defines the number of initial wait cycles at the start of a new line by the Framing logic. This allows enough data to be buffered in the input FIFO. The default value of INIT_WAIT is 0x20.

If (MIN_BYTES_PER_TU ≤ 4)

  • [6:0] - Set INIT_WAIT to 64

Else if color format is RGB/YCbCr_444/YCbCr_420

  • [6:0] - Set INIT_WAIT to (TRANSFER_UNIT_SIZE - MIN_BYTES_PER_TU)

Else if color format is YCbCr_422

  • [6:0] - Set INIT_WAIT to (TRANSFER_UNIT_SIZE - MIN_BYTES_PER_TU)/2

Else if color format is Y_Only

  • [6:0] - Set INIT_WAIT to (TRANSFER_UNIT_SIZE - MIN_BYTES_PER_TU)/3