Source Core Setup - 3.1 English

DisplayPort 1.4 TX Subsystem Product Guide

Document ID

PG299

Release Date

2022-10-19

Version

3.1 English

Place the PHY into reset.
Disable the transmitter.
```
TRANSMITTER_ENABLE = 0x00
```

Set the clock divider.

AUX_CLOCK_DIVIDER = (see register description for proper value)

Select and set up the reference clock for the desired link rate in the Video PHY Controller.
Bring the PHY out of reset.
Wait for the PHY to be ready.
Enable the transmitter.
```
TRANSMITTER_ENABLE = 0x01
```
(Optional) Turn on the interrupt mask for HPD.
```
INTERRUPT_MASK = 0x00
```

At this point, the source core is initialized and ready to use. The link policy maker should be monitoring the status of HPD and taking appropriate action for connect/disconnect events or HPD interrupt pulses.